AD5662 datasheet(8/36 Pages) AD

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AD5750/AD5750-1/AD5750-2

Data Sheet

Rev. D | Page 8 of 36

TIMING CHARACTERISTICS

AVDD/AVSS = ±12 V (± 10%) to ±24 V (± 10%), DVCC = 2.7 V to 5.5 V, GND = 0 V. VOUT: RLOAD = 2 kΩ, CL = 200 pF, IOUT: RLOAD =

300 Ω. All specifications TMIN to TMAX, unless otherwise noted.

Table 3.

Parameter1, 2

Limit at TMIN, TMAX

Unit

Description

t1

20

ns min

SCLK cycle time

t2

8

ns min

SCLK high time

t3

8

ns min

SCLK low time

t4

5

ns min

SYNC falling edge to SCLK falling edge setup time

t5

10

ns min

16th SCLK falling edge to SYNC rising edge (on 24th SCLK falling edge if using PEC)

t6

5

ns min

Minimum SYNC high time (write mode)

t7

5

ns min

Data setup time

t8

5

ns min

Data hold time

t9, t10

1.5

µs max

CLEAR pulse low/high activation time

t11

5

ns min

Minimum SYNC high time (read mode)

t12

40

ns max

SCLK rising edge to SDO valid (SDO CL = 15 pF)

t13

10

ns min

RESET pulse low time

1

Guaranteed by characterization, but not production tested.

2

All input signals are specified with tR = tF = 5 ns (10% to 90% of DVCC) and timed from a voltage level of 1.2 V.

Số phần tương tự - AD5662

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
Analog Devices	AD5662	357Kb / 20P	2.7 V to 5.5 V, 250 uA, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23 Rev. PrA
	AD5662ARJ-1	357Kb / 20P	2.7 V to 5.5 V, 250 uA, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23 Rev. PrA
	AD5662ARJ-1500RL7	584Kb / 24P	16-Bit nanoDAC in a SOT-23 REV. A
	AD5662ARJ-1REEL7	584Kb / 24P	16-Bit nanoDAC in a SOT-23 REV. A
	AD5662ARJ-2	357Kb / 20P	2.7 V to 5.5 V, 250 uA, Rail-to-Rail Output 16-Bit DAC D/A in a SOT-23 Rev. PrA

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Mô tả tương tự - AD5662

nhà sản xuất	tên linh kiện	bảng dữ liệu	Giải thích chi tiết về linh kiện
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