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MCM6706BRJ7R bảng dữ liệu(PDF) 5 Page - Motorola, Inc |
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MCM6706BRJ7R bảng dữ liệu(HTML) 5 Page - Motorola, Inc |
5 / 7 page MCM6706BR 5 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) 6706BR–6 6706BR–7 6706BR–8 Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 6 — 7 — 8 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 6 — 7 — 8 — ns Write Pulse Width tWLWH, tWLEH 6 — 7 — 8 — ns Data Valid to End of Write tDVWH 3 — 3.5 — 3.5 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ — 3.5 — 3.5 — 3.5 ns 4, 5, 6 Write High to Output Active tWHQX 3 — 3 — 3 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady–state voltage with load of Figure 1b. 5. Parameter is sampled and not 100% tested. 6. At any given voltage and temperature, tWLQZ max is < tWHQX min both for a given device and from device to device. WRITE CYCLE 1 Q (DATA OUT) D (DATA IN) W (WRITE ENABLE) E (CHIP ENABLE) A (ADDRESS) DATA VALID HIGH–Z tAVAV tWHDX tWHQX HIGH–Z tWHAX tAVWH tWLQZ tAVWL tDVWH tWLWH tWLEH |
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