MCM6706BR

6

MOTOROLA FAST SRAM

6706BR–6

6706BR–7

6706BR–8

Parameter

Symbol

Min

Max

Min

Max

Min

Max

Unit

Notes

Write Cycle Time

tAVAV

6

—

7

—

8

—

ns

3

Address Setup Time

tAVEL

0

—

0

—

0

—

ns

Address Valid to End of Write

tAVEH

6

—

7

—

8

—

ns

Chip Enable to End of Write

tELWH,

tELEH

5

—

6

—

6

—

ns

4,5

Data Valid to End of Write

tDVEH

3

—

3.5

—

3.5

—

ns

Data Hold Time

tEHDX

0

—

0

—

0

—

ns

Write Recovery Time

tEHAX

0

—

0

—

0

—

ns

NOTES:

1. A write occurs during the overlap of E low and W low.

2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus

contention conditions during read and write cycles.

3. All write cycle timing is referenced from the last valid address to the first transitioning address.

4. If E goes low coincident with or after W goes low, the output will remain in a high impedance condition.

5. If E goes high coincident with or before W goes high, the output will remain in a high impedance condition.

WRITE CYCLE 2

W (WRITE ENABLE)

Q (DATA OUT)

D (DATA IN)

E (CHIP ENABLE)

A (ADDRESS)

HIGH–Z

tAVAV

DATA VALID

tEHDX

tDVEH

tEHAX

tELWH

tAVEH

tAVEL

tELEH

ORDERING INFORMATION

(Order by Full Part Number)

Motorola Memory Prefix

Part Number

Package (J = 300 mil SOJ)

Full Part Numbers — MCM6706BRJ6

MCM6706J7

MCM6706BRJ8

MCM6706BRJ6R

MCM6706BRJ7R

MCM6706BRJ8R

Shipping Method (R = Tape and Reel, Blank = Rails)

Speed (6 = 6 ns, 7 = 7 ns, 8 = 8 ns)

MCM 6706BR

X

X

XX