MCM64PD32

•MCM64PD64

6

MOTOROLA FAST SRAM

CCS

ADSP

CADS

CADV

CWEx

CLK0

Address Used

Operation

H

X

L

X

X

L–H

N/A

Deselected

L

L

X

X

X

L–H

External Address

Read Cycle, Begin Burst

L

H

L

X

L

L–H

External Address

Write Cycle, Begin Burst

L

H

L

X

H

L–H

External Address

Read Cycle, Begin Burst

X

H

H

L

L

L–H

Next Address

Write Cycle, Continue Burst

X

H

H

L

H

L–H

Next Address

Read Cycle, Continue Burst

X

H

H

H

L

L–H

Current Address

Write Cycle, Suspend Burst

X

H

H

H

H

L–H

Current Address

Read Cycle, Suspend Burst

H

X

H

L

L

L–H

Next Address

Write Cycle, Continue Burst

H

X

H

L

H

L–H

Next Address

Read Cycle, Continue Burst

H

X

H

H

L

L–H

Current Address

Write Cycle, Suspend Burst

H

X

H

H

H

L–H

Current Address

Read Cycle, Suspend Burst

NOTES:

1. X means Don’t Care.

2. All inputs except CG must meet setup and hold times for the low–to–high transition of clock (CLK0/1).

3. Wait states are inserted by suspending burst.

Operation

CG

I/O Status

Read

L

Data Out

Read

H

High–Z

Write

X

High–Z — Data In

Deselected

X

High–Z

NOTES:

1. X means Don’t Care.

2. For a write operation following a read operation, G must be high before the input data

required setup time and held high through the input data hold time.

Rating

Symbol

Value

Unit

Power Supply Voltage

VDD3

– 0.5 to + 4.6

V

Voltage Relative to VSS

Vin, Vout

VSS – 0.5 to VDD3 + 0.5

V

Output Current (per I/O)

Iout

± 20

mA

Temperature Under Bias

Tbias

– 10 to + 85

°C

Operating Temperature

TA

0 to +70

°C

Storage Temperature

Tstg

– 65 to + 150

°C

NOTE: Permanent device damage may occur if ABSOLUTE MAXIMUM RATINGS are

exceeded. Functional operation should be restricted to RECOMMENDED OPER-

ATING CONDITIONS. Exposure to higher than recommended voltages for

extended periods of time could affect device reliability.

This device contains circuitry to protect the

inputs against damage due to high static volt-

ages or electric fields; however, it is advised

that normal precautions be taken to avoid

application of any voltage higher than maxi-

mum rated voltages to this high–impedance

circuit.

This BiCMOS memory circuit has been

designed to meet the dc and ac specifications

shown in the tables, after thermal equilibrium

has been established.

This device contains circuitry that will

ensure the output devices are in High–Z at

power up.