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MCM63P733ATQ90 bảng dữ liệu(PDF) 8 Page - Motorola, Inc

tên linh kiện MCM63P733ATQ90
Giải thích chi tiết về linh kiện  128K x 32 Bit Pipelined BurstRAM Synchronous Fast Static RAM
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

MCM63P733ATQ90 bảng dữ liệu(HTML) 8 Page - Motorola, Inc

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MCM63P733A
8
MOTOROLA FAST SRAM
SUPPLY CURRENTS
Parameter
Symbol
Min
Typ
Max
Unit
Notes
Input Leakage Current (0 V
≤ Vin ≤ VDD)
Ilkg(I)
± 1
µA
1, 2
Output Leakage Current (0 V
≤ Vin ≤ VDDQ)
Ilkg(O)
± 1
µA
AC Supply Current (Device Selected,
MCM63P733A–133
All Outputs Open, Freq = Max)
MCM63P733A–117
Includes VDD Only
MCM63P733A–100
MCM63P733A–90
IDDA
TBD
mA
3, 4, 5
CMOS Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at CMOS Levels)
ISB2
TBD
mA
6, 8
Sleep Mode Supply Current (Sleep Mode, Freq = Max,
VDD = Max, All Other Inputs Static at CMOS Levels,
ZZ
≥ VDD – 0.2 V)
IZZ
2
mA
2, 7, 8
TTL Standby Supply Current (Device Deselected, Freq = 0,
VDD = Max, All Inputs Static at TTL Levels)
ISB3
TBD
mA
6, 9
Clock Running (Device Deselected,
MCM63P733A–133
Freq = Max, VDD = Max, All Inputs
MCM63P733A–117
Toggling at CMOS Levels)
MCM63P733A–100
MCM63P733A–90
ISB4
TBD
mA
3, 4,
5, 6, 8
Static Clock Running (Device Deselected, MCM63P733A–133
Freq = Max, VDD = Max, All Inputs
MCM63P733A–117
Static at TTL Levels)
MCM63P733A–100
MCM63P733A–90
ISB5
TBD
mA
6, 9
NOTES:
1. LBO pin has an internal pullup and will exhibit leakage currents of
± 5 µA.
2. ZZ pin has an internal pulldown and will exhibit leakage currents of
± 5 µA.
3. Reference AC Operating Conditions and Characteristics for input and timing.
4. All addresses transition simultaneously low (LSB) then high (MSB).
5. Data states are all zero.
6. Device is deselected as defined by the Truth Table.
7. Device in Sleep Mode as defined by the Asynchronous Truth Table.
8. CMOS levels for I/O’s are VIT ≤ VSS + 0.2 V or ≥ VDDQ – 0.2 V. CMOS levels for other inputs are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V.
9. TTL levels for I/O’s are VIT ≤ VIL or ≥ VIH2. TTL levels for other inputs are Vin ≤ VIL or ≥ VIH.
CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested)
Parameter
Symbol
Min
Typ
Max
Unit
Input Capacitance
Cin
4
5
pF
Input/Output Capacitance
CI/O
7
8
pF


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