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MCM63P631TQ8 bảng dữ liệu(PDF) 8 Page - Motorola, Inc |
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MCM63P631TQ8 bảng dữ liệu(HTML) 8 Page - Motorola, Inc |
8 / 16 page MCM63P631 8 MOTOROLA FAST SRAM DC OPERATING CONDITIONS AND CHARACTERISTICS (VDD = 3.3 V + 10%, – 5%, TA = 0 to 70°C, Unless Otherwise Noted) RECOMMENDED OPERATING CONDITIONS (Voltages Referenced to VSS = 0 V) Parameter Symbol Min Typ Max Unit Supply Voltage VDD 3.135 3.3 3.6 V Input Low Voltage VIL – 0.5* — 0.8 V Input High Voltage VIH 2.0** — VDD + 0.5 V *VIL ≥ – 1 V for t ≤ tKHKH/2. ** VIH ≤ VDD + 1 V for t ≤ tKHKH/2. DC CHARACTERISTICS AND SUPPLY CURRENTS Parameter Symbol Min Typ Max Unit Notes Input Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(I) — — ± 1 µA 1, 2 Output Leakage Current (0 V ≤ Vin ≤ VDD) Ilkg(O) — — ± 1 µA AC Supply Current (Device Selected, All Outputs Open, MCM63P631–117 Freq = Max, VDD = Max) MCM63P631–4.5 MCM P IDDA — — — — TBD 275 220 mA 3, 4, 5 q DD ) MCM63P631–7 MCM63P631–8 — — — — 220 200 CMOS Standby Supply Current (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at CMOS Levels) ISB2 — — 2 mA 6, 7 Sleep Mode Supply Current (Sleep Mode, Freq = Max, VDD = Max, All Other Inputs Static at CMOS Levels, ZZ ≥ VDD – 0.2 V) IZZ — — 2 mA 2, 7, 8 TTL Standby (Device Deselected, Freq = 0, VDD = Max, All Inputs Static at TTL Levels) ISB3 — — 25 mA 6, 9 Clock Running (Device Deselected, Freq = Max, MCM63P631–117 VDD = Max, All Inputs Toggling at CMOS Levels) MCM63P631–4.5 MCM P ISB4 — — — — TBD 145 mA 6, 7 DD pgg g ) MCM63P631–7 MCM63P631–8 — — — — 115 105 Static Clock Running (Device Deselected, Freq = Max, MCM63P631–117 VDD = Max, All Inputs Static at TTL Levels) MCM63P631–4.5 MCM63P631–7 MCM63P631–8 ISB5 — — — — — — — — TBD 65 50 50 mA 6, 9 Output Low Voltage (IOL = 8 mA) VOL — — 0.4 V Output High Voltage (IOH = – 4 mA) VOH 2.4 — — V NOTES: 1. LBO pin has an internal pullup and will exhibit leakage currents of ± 5 µA. 2. ZZ pin has an internal pulldown and will exhibit leakage currents of ± 5 µA. 3. Reference AC Operating Conditions and Characteristics for input and timing (VIH/VIL, tr/tf, pulse level 0 to 3.0 V). 4. All addresses transition simultaneously low (LSB) and then high (MSB). 5. Data states are all zero. 6. Device in Deselected mode as defined by the Truth Table. 7. CMOS levels are Vin ≤ VSS + 0.2 V or ≥ VDD – 0.2 V. 8. Device in Sleep Mode as defined by the Asynchronous Truth Table. 9. TTL levels are Vin ≤ VIL or ≥ VIH. CAPACITANCE (f = 1.0 MHz, dV = 3.0 V, TA = 0 to 70°C, Periodically Sampled Rather Than 100% Tested) Parameter Symbol Min Typ Max Unit Input Capacitance Cin — 3 5 pF Input/Output Capacitance CI/O — 6 8 pF |
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