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MCM6229BBEJ35R2 bảng dữ liệu(PDF) 5 Page - Motorola, Inc |
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MCM6229BBEJ35R2 bảng dữ liệu(HTML) 5 Page - Motorola, Inc |
5 / 8 page MCM6229BB 5 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1, 2, 3, and 4) 6229BB–15 6229BB–17 6229BB–20 6229BB–25 6229BB–35 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 15 — 17 — 20 — 25 — 35 — ns 4 Address Setup Time tAVWL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 12 — 14 — 15 — 17 — 20 — ns Write Pulse Width tWLWH, tWLEH 12 — 14 — 15 — 17 — 20 — ns Data Valid to End of Write tDVWH 7 — 8 — 9 — 10 — 11 — ns Data Hold TIme tWHDX 0 — 0 — 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ — 6 — 7 — 7 — 8 — 8 ns 5, 6, 7 Write High to Output Active tWHQX 5 — 5 — 5 — 5 — 5 — ns 5, 6, 7 Write Recovery Time tWHAX 0 — 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus con- tention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All timings are referenced from the last valid address to the first transitioning address. 5. Transition is measured ± 500 mV from steady–state voltage with load of Figure 1b. 6. This parameter is sampled and not 100% tested. 7. At any given voltage and temperature, tWLQZ max is less than tWHQX min both for a given device and from device to device. WRITE CYCLE 1 (W Controlled See Notes 1, 2, 3, and 4) tAVWH tWLQZ tWHAX tDVWH A (ADDRESS) E (CHIP ENABLE) W (WRITE ENABLE) D (DATA IN) Q (DATA OUT) DATA VALID HIGH–Z HIGH–Z tAVAV tAVWL tWLEH tWHDX tWLWH tWHQX |
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