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MCM6343YJ12 bảng dữ liệu(PDF) 8 Page - Motorola, Inc |
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MCM6343YJ12 bảng dữ liệu(HTML) 8 Page - Motorola, Inc |
8 / 10 page MCM6343 8 MOTOROLA FAST SRAM WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3) P Sb l MCM6343–12 MCM6343–15 Ui N Parameter Symbol Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — ns 4 Address Setup Time tAVBL 0 — 0 — ns Address Valid to End of Write tAVBH 10 — 12 — ns Address Valid to End of Write (G High) tAVBH 9 — 10 — ns Byte Pulse Width tBLWH tBLEH 10 — 12 — ns Byte Pulse Width (G High) tBLWH tBLEH 9 — 10 — ns Data Valid to End of Write tDVBH 6 — 7 — ns Data Hold Time tBHDX 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. Product sensitivities to noise require proper grounding and decoupling of power supplies as well as minimization or elimination of bus contention conditions during read and write cycles. 3. If G goes low coincident with or after W goes low, the output will remain in a high–impedance state. 4. All write cycle timings are referenced from the last valid address to the first transitioning address. DATA VALID tDVBH tAVBL tAVBH tAVAV tBLWH tBHDX HIGH–Z HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) tBLEH LB, UB (BYTE ENABLE) WRITE CYCLE 3 (E Controlled; See Notes 1, 2, and 3) |
Số phần tương tự - MCM6343YJ12 |
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Mô tả tương tự - MCM6343YJ12 |
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