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MCM6323AYJ10R bảng dữ liệu(PDF) 7 Page - Motorola, Inc |
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MCM6323AYJ10R bảng dữ liệu(HTML) 7 Page - Motorola, Inc |
7 / 12 page MCM6323A 7 MOTOROLA FAST SRAM WRITE CYCLE 1 (W Controlled, See Notes 1 and 2) P Sb l MCM6323A–10 MCM6323A–12 MCM6323A–15 Ui N Parameter Symbol Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 10 — 12 — 15 — ns 3 Address Setup Time tAVWL 0 — 0 — 0 — ns Address Valid to End of Write tAVWH 8 — 9 — 10 — ns Write Pulse Width tWLWH, tWLEH 8 — 9 — 10 — ns Byte Pulse Width tBLWH, tBLEH 8 — 9 — 10 — ns Data Valid to End of Write tDVWH 4 — 5 — 6 — ns Data Hold Time tWHDX 0 — 0 — 0 — ns Write Low to Data High–Z tWLQZ 0 4 0 5 0 6 ns 4, 5, 6 Write High to Output Active tWHQX 3 — 3 — 3 — ns 4, 5, 6 Write Recovery Time tWHAX 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low, W low, and LB and/or UB low. 2. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycles. 3. All write cycle timings are referenced from the last valid address to the first transitioning address. 4. Transition is measured 200 mV from steady–state voltage. 5. At any given voltage and temperature, tWLQZ max < tWHQX min both for a given device and from device to device. 6. This parameter is sampled and not 100% tested. WRITE CYCLE 1 (W Controlled) DATA VALID tDVWH tAVWL tAVWH tAVAV tWHAX tWLWH tWHDX tWLQZ tWHQX HIGH–Z HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) tWLEH tBLWH LB, UB (BYTE ENABLE) tBLEH |
Số phần tương tự - MCM6323AYJ10R |
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