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MCM6265CJ12 bảng dữ liệu(PDF) 6 Page - Motorola, Inc |
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MCM6265CJ12 bảng dữ liệu(HTML) 6 Page - Motorola, Inc |
6 / 8 page MCM6265C 6 MOTOROLA FAST SRAM WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) – 12 – 15 – 20 – 25 – 35 Parameter Symbol Min Max Min Max Min Max Min Max Min Max Unit Notes Write Cycle Time tAVAV 12 — 15 — 20 — 25 — 35 — ns 3 Address Setup Time tAVEL 0 — 0 — 0 — 0 — 0 — ns Address Valid to End of Write tAVEH 12 — 12 — 15 — 20 — 25 — ns Enable to End of Write tELEH, tELWH 10 — 10 — 12 — 15 — 25 — ns 4, 5 Write Pulse Width tWLEH 10 — 12 — 15 — 17 — 20 — ns Data Valid to End of Write tDVEH 7 — 7 — 8 — 10 — 15 — ns Data Hold Time tEHDX 0 — 0 — 0 — 0 — 0 — ns Write Recovery Time tEHAX 0 — 0 — 0 — 0 — 0 — ns NOTES: 1. A write occurs during the overlap of E low and W low. 2. E1 and E2 are represented by E in this data sheet. E2 is of opposite polarity to E. 3. All timings are referenced from the last valid address to the first transitioning address. 4. If E goes low coincident with or after W goes low, the output will remain in a high impedance state. 5. If E goes high coincident with or before W goes high, the output will remain in a high impedance state. WRITE CYCLE 2 (E Controlled, See Notes 1 and 2) tEHDX tDVEH tEHAX tELEH tELWH tWLEH tAVEL tAVEH DATA VALID tAVAV HIGH–Z A (ADDRESS) W (WRITE ENABLE) E (CHIP ENABLE) Q (DATA OUT) D (DATA IN) |
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