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AZP52SG bảng dữ liệu(PDF) 2 Page - Arizona Microtek, Inc |
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AZP52SG bảng dữ liệu(HTML) 2 Page - Arizona Microtek, Inc |
2 / 9 page Arizona Microtek, Inc. AZP52 Low Phase Noise Sine Wave/CMOS to LVPECL Buffer/Divider www.azmicrotek.com +1-480-962-5881 2 Request a Sample May 2012, Rev 2.1 PIN DESCRIPTION AND CONFIGURATION Table 1 - Pin Description Pin Name Type Function 1 VDD Power Positive Supply 2 GND Power Negative Supply 3 D Input Sine or CMOS Input 4 EN Input Enable 5 Q Output LVPECL Output 6 Q Output LVPECL Output ENGINEERING NOTES FUNCTIONALITY The AZP52 is one of a family of parts that provide options of fixed ÷1, fixed ÷2 and selectable ÷1, ÷2 modes as well as active high enable or active low enable to oscillator designers. Table 2 details the differences between the parts to assist designers in selecting the optimal part for their design. Table 3 lists the specific AZP52 functional operation. Figure 2 plots the S-parameters of the D input. S-parameter and IBIS model files for the AZP52 are also available for download. Table 2 - AZP51-54 & AZP63 Family Part Number Divide Ratio EN Logic EN pull- up/pull-down Bandwidth AZP51 ÷1 active HIGH Pull-up > 800MHz AZP52 ÷2 active HIGH Pull-up > 800MHz AZP53 Selectable ÷1 or ÷2 selectable selectable > 800MHz AZP54 ÷1 active LOW Pull-down > 800MHz AZP63 Selectable ÷1 or ÷2 selectable selectable ≥ 1GHz Figure 1 – Pin Configuration 1 VDD 3 D 2 GND 6 Q 4 EN 5 Q |
Số phần tương tự - AZP52SG |
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Mô tả tương tự - AZP52SG |
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