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MCM62486BFN19 bảng dữ liệu(PDF) 1 Page - Motorola, Inc |
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1 / 12 page MCM62486B 1 MOTOROLA FAST SRAM 32K x 9 Bit BurstRAM ™ Synchronous Static RAM With Burst Counter and Self–Timed Write The MCM62486B is a 294,912 bit synchronous static random access memory designed to provide a burstable, high–performance, secondary cache for the i486 and Pentium ™ microprocessors. It is organized as 32,768 words of 9 bits, fabricated with Motorola’s high–performance silicon–gate CMOS technology. The device integrates input registers, a 2–bit counter, high speed SRAM, and high drive capability outputs onto a single monolithic circuit for re- duced parts count implementation of cache data RAM applications. Synchro- nous design allows precise cycle control with the use of an external clock (K). CMOS circuitry reduces the overall power consumption of the integrated func- tions for greater reliability. Addresses (A0 – A14), data inputs (D0 – D8), and all control signals except output enable (G) are clock (K) controlled through positive–edge–triggered noninverting registers. Bursts can be initiated with either address status processor (ADSP) or address status cache controller (ADSC) input pins. Subsequent burst addresses can be generated internally by the MCM62486B (burst sequence imitates that of the i486 and Pentium) and controlled by the burst address advance (ADV) input pin. The following pages provide more detailed information on burst controls. Write cycles are internally self–timed and are initiated by the rising edge of the clock (K) input. This feature eliminates complex off–chip write pulse generation and provides increased flexibility for incoming signals. The MCM62486B will be available in a 44–pin plastic leaded chip carrier (PLCC). Multiple power and ground pins have been utilized to minimize effects induced by output noise. Separate power and ground pins have been employed for DQ0 – DQ8 to allow user–controlled output levels of 5 volts or 3.3 volts. • Single 5 V ± 10% Power Supply (± 5% for MCM62486BFN11) • Choice of 5 V or 3.3 V ± 10% Power Supplies for Output Level Compatibility • Fast Access Times:11/12/14/19 ns Max and Cycle Times:15/20/25 ns Min • Internal Input Registers (Address, Data, Control) • Internally Self–Timed Write Cycle • ADSP, ADSC, and ADV Burst Control Pins • Asynchronous Output Enable Controlled Three–State Outputs • Common Data Inputs and Data Outputs • High Output Drive Capability: 85 pF per I/O • High Board Density PLCC Package • Fully TTL–Compatible • Active High and Low Chip Select Inputs for Easy Depth Expansion BurstRAM is a trademark of Motorola, Inc. i486 and Pentium are trademarks of Intel Corp. Order this document by MCM62486B/D MOTOROLA SEMICONDUCTOR TECHNICAL DATA FN PACKAGE 44–LEAD PLCC CASE 777–01 MCM62486B PIN NAMES PIN ASSIGNMENT A11 A12 A13 A14 DQ7 DQ6 DQ5 DQ4 A2 A3 A4 A5 A6 DQ0 DQ1 DQ2 VSS VSSQ VCCQ VSS VSSQ VCCQ A0 – A14 Address Inputs . . . . . . . . . . . . . . . . K Clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . W Write Enable . . . . . . . . . . . . . . . . . . . . . . . . G Output Enable . . . . . . . . . . . . . . . . . . . . . . S0, S1 Chip Selects . . . . . . . . . . . . . . . . . . . . ADV Burst Address Advance . . . . . . . . . . . . ADSP, ADSC Address Status . . . . . . . . . . . . DQ0 – DQ8 Data Input/Output . . . . . . . . . . . VCC + 5 V Power Supply . . . . . . . . . . . . . . . . VCCQ Output Buffer Power Supply . . . . . . . VSS Ground . . . . . . . . . . . . . . . . . . . . . . . . . . VSSQ Output Buffer Ground . . . . . . . . . . . . All power supply and ground pins must be con- nected for proper operation of the device. VCC ≥ VCCQ at all times including power up. 6 5 4 3 2 1 44 43 42 41 40 10 9 8 12 11 15 14 13 17 16 7 32 33 29 30 31 35 36 34 37 38 39 18 19 20 21 22 23 24 25 26 27 28 REV 2 5/95 © Motorola, Inc. 1994 |
Số phần tương tự - MCM62486BFN19 |
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Mô tả tương tự - MCM62486BFN19 |
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