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MCM62486BFN19 bảng dữ liệu(PDF) 5 Page - Motorola, Inc

tên linh kiện MCM62486BFN19
Giải thích chi tiết về linh kiện  32K x 9 Bit BurstRAM Synchronous Static RAM
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nhà sản xuất  MOTOROLA [Motorola, Inc]
Trang chủ  http://www.freescale.com
Logo MOTOROLA - Motorola, Inc

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MCM62486B
5
MOTOROLA FAST SRAM
AC OPERATING CONDITIONS AND CHARACTERISTICS
(VCC, VCCQ = 5.0 V ± 5%, TA = 0 to + 70°C, for device MCM62486B–11)
(VCC = 5.0 V ± 10%, VCCQ = 5.0 V or 3.3 V ± 10%, TA = 0 to + 70°C, for all other devices)
Input Timing Measurement Reference Level
1.5 V
. . . . . . . . . . . . . . .
Input Pulse Levels
0 to 3.0 V
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Input Rise/Fall Time
3 ns
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Output Timing Reference Level
1.5 V
. . . . . . . . . . . . . . . . . . . . . . . . . .
Output Load
Figure 1A Unless Otherwise Noted
. . . . . . . . . . . . . . . .
READ/WRITE CYCLE TIMING (See Notes 1, 2, and 3)
62486B–11
62486B–12
62486B–14
62486B–19
Parameter
Symbol
Min
Max
Min
Max
Min
Max
Min
Max
Unit
Notes
Cycle Time
tKHKH
15
20
20
25
ns
Clock Access Time
tKHQV
11
12
14
19
ns
Output Enable Access
tGLQV
5
5
6
7
ns
Clock High to Output Active
tKHQX1
6
6
6
6
ns
Clock High to Q Change
tKHQX2
3
3
4
4
ns
Output Enable to Q Active
tGLQX
0
0
0
0
ns
Output Disable to Q High–Z
tGHQZ
6
6
6
7
ns
4
Clock High to Q High–Z
tKHQZ
6
6
6
6
ns
Clock High Pulse Width
tKHKL
5.5
7
8
6
ns
Clock Low Pulse Width
tKLKH
5.5
7
8
6
ns
Setup Times:
Address
Address Status
Data In
Write
Address Advance
Chip Select
tAVKH
tADSVKH
tDVKH
tWVKH
tADVVKH
tS0VKH
tS1VKH
2
2
3
3
ns
5
Hold Times:
Address
Address Status
Data In
Write
Address Advance
Chip Select
tKHAX
tKHADSX
tKHDX
tKHWX
tKHADVX
tKHS0X
tKHS1X
2
2
2
2
ns
5
NOTES:
1. A read cycle is defined by W high or ADSP low for the setup and hold times. A write cycle is defined by W low and ADSP high for the setup
and hold times.
2. All read and write cycle timings are referenced from K or G.
3. G is a don’t care when W is sampled low.
4. Transition is measured
± 500 mV from steady–state voltage with load of Figure 1B. This parameter is sampled and not 100% tested. At any
given voltage and temperature, tKHQZ max is less than tKHQX1 min for a given device and from device to device.
5. This is a synchronous device. All addresses must meet the specified setup and hold times for
ALL rising edges of clock (K) whenever ADSP
and ADSC are low and the chip is selected. All other synchronous inputs must meet the specified setup and hold times for
ALL rising edges
of K when the chip is selected.Chip select must be true (S1 low and S0 high) at each rising edge of clock for the device (when ADSP or ADSC
is low) to remain enabled. Timings for S1 and S0 are similar.
AC TEST LOADS
Figure 1B
5 pF
+ 5 V
OUTPUT
255
480
Figure 1A
OUTPUT
Z0 = 50 Ω
RL = 50 Ω
VL = 1.5 V


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