MOTOROLA

SEMICONDUCTOR TECHNICAL DATA

1

REV 4

1/97

Not Recommended for New Designs

CMOS PLL Clock Driver

Programmable Frequency, Low Skew,

High Fan-Out

The MC88PL117 utilizes proven phase–locked loop clock driver

technology to create a large fan–out, multiple frequency and phase, low

skew clock driver. The 88PL117 provides the clock frequencies

necessary to drive systems using the PowerPC

™ 601 microprocessor

and the Pentium

™ microprocessor (see applications section for details).

A total of 14 high current, matched impedance outputs are available in 8

programmable output frequency and phase configurations. Output

frequencies are referenced to a system frequency, Q, and are available at

2X, 1X, and 1/2X the Q frequency. Four programmable input frequency

multiplication ratios can be programmed to provide outputs at 1X, 2X, and

4X the system frequency Q. Details on the programmable configurations

can be found in the applications section of this data sheet.

phase–lock is achieved

One output (QFEED) is dedicated for feedback. It is located physically close to the FEEDBACK input pin to minimize the

feedback line length. External delay (increased wire length) or logic can be inserted in the feedback path if necessary. Proper

termination of the feedback line is necessary for any line length over one inch.

One output is provided with up to eight selectable 1/8 or 1/4 period (45

° or 90°) delay increments. Three control pins, ∅2, ∅1

and

∅0, program the eight increments; the increment/phase shift positions are shown in Table 3. in the applications section.

All outputs can be 3–stated (high impedance) during board–level testing with the OE/MR pin; the QFEED and LOCK outputs

will not be 3–stated, which allows the 88PL117 to remain in a phase–locked condition. Correct phase and frequency coherency

will be guaranteed one to two cycles after bringing the OE/MR pin high. The PLL_EN pin disables the PLL and gates the SYNC

input signal directly into the internal clock distribution network to provide low frequency testability. Two selectable SYNC inputs

(SYNC0 and SYNC1) are provided for clock redundancy or ease of testability. The device is guaranteed to lock to the new SYNC

input when the REF_SEL input is switched dynamically.

A phase–lock indicator output (LOCK) stays low when the part is out of lock (start–up, etc.) and goes high when steady–state

phase–lock is achieved. The lock indicator circuitry works reliably for VCO frequencies down to 55MHz. For VCO frequencies

less than 55MHz, no guarantees are offered for the lock indicator output.

The MC88PL117 VCO is capable of operating at frequencies higher than the output divider and feedback structures are able

to follow. When the VCO is in the mode described above, it is referred to as “runaway” and the device will not lock. The condition

usually occurs at power–up. To avoid runaway, it is recommended that the device be fully powered before a sync signal is

applied.

PowerPC is a trademark of International Business Machines Corporation.

MC88PL117

CMOS PLL

CLOCK DRIVER

FN SUFFIX

52–LEAD PLASTIC LEADLESS

CHIP CARRIER (PLCC)

CASE 778–02