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MC88916DWR2 bảng dữ liệu(PDF) 7 Page - Motorola, Inc

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Giải thích chi tiết về linh kiện  LOW SKEW CMOS PLL CLOCK DRIVER WITH PROCESSOR RESET
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nhà sản xuất  MOTOROLA [Motorola, Inc]
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MC88916
TIMING SOLUTIONS
BR1333 — REV 5
7
MOTOROLA
Figure 3. MC68040 PCLK Input Termination Scheme
88916
2X_Q
OUTPUT
68040
PCLK
CLOCK
INPUT
Rs = Zo – 7
Rs
Zo (CLOCK
TRACE)
Figure 5. Logical Representation of the MC88916 With
Input/Output Frequency Relationships
2X_Q
Q0
Q1
Q2
Q3
Q/2
RST_OUT
SYNC
MR
PLL_EN
RST_IN
16.5MHz
CRYSTAL
OSCILLATOR
66MHz PCLK OUTPUT
33MHz
B–CLOCK
AND SYSTEM
OUTPUTS
ANALOG GND
CL
VCC
1K
RST_OUT PIN
INTERNAL
LOGIC
Figure 4. RST_OUT Test Circuit
RP
RP = 1.5Zo
Figure 6. Output/Input Switching Waveforms and Timing Relationships
SYNC Input
Q0–Q2 Outputs
Q3 Output
2X_Q Output
Q/2 Output
tCYCLE SYNC Input
tSKEWall
tSKEWf
tSKEWr
tSKEWf
tSKEWr
tCYCLE ‘Q’ Outputs
Timing Notes
1. The MC88916 aligns rising edges of the outputs and the SYNC input, therefore the SYNC input does not require a 50%
duty cycle.
2. All skew specs are measured between the VCC/2 crossing point of the appropriate output edges. All skews are specified as
‘windows’, not as a
± deviation around a center point.


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