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ISLA214S35IR1Z bảng dữ liệu(PDF) 4 Page - Intersil Corporation

tên linh kiện ISLA214S35IR1Z
Giải thích chi tiết về linh kiện  14-Bit, 500/350 MSPS JESD204B High Speed Serial Output ADC
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nhà sản xuất  INTERSIL [Intersil Corporation]
Trang chủ  http://www.intersil.com/cda/home
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ISLA214S50
4
FN7973.1
December 21, 2011
Table of Contents
Pin Descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . . . . . . . . . 5
Thermal Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Recommended Operating Conditions. . . . . . . . . . . . . . . . . 5
Digital Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Switching Specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Typical Performance Curves. . . . . . . . . . . . . . . . . . . . . . . 10
Theory of Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Power-On Calibration . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
User Initiated Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Temperature Calibration. . . . . . . . . . . . . . . . . . . . . . . . . . 16
Analog Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Clock Input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Jitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Digital Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Power Dissipation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Nap/Sleep . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
I2E Requirements and Restrictions. . . . . . . . . . . . . . . . . 20
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Active Run State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Power Meter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
FS/4 Filter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Nyquist Zones . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Configurability and Communication . . . . . . . . . . . . . . 20
Clock Divider Synchronous Reset . . . . . . . . . . . . . . . . . . 21
Soft Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
JESD204A Transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21
Initial Lane Alignment. . . . . . . . . . . . . . . . . . . . . . . . . . 22
Test Patterns . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Serial Peripheral Interface . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI Physical Interface . . . . . . . . . . . . . . . . . . . . . . . . . . 26
SPI Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Device Configuration/Control. . . . . . . . . . . . . . . . . . . . 27
Address 0x60-0x64: I2E initialization . . . . . . . . . . . . . 29
Global Device Configuration/Control . . . . . . . . . . . . . 30
ADDRESS 0xDF - 0xF3: JESD204 REGISTERS . . . . . . 31
Address 0xDF-0xEE: JESD204A Parameter
INTERFACE 31
SPI Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Equivalent Circuits. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
ADC Evaluation Platform . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Layout Considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Split Ground and Power Planes . . . . . . . . . . . . . . . . . . 39
Clock Input Considerations. . . . . . . . . . . . . . . . . . . . . . 39
Exposed Paddle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Bypass and Filtering . . . . . . . . . . . . . . . . . . . . . . . . . . . .39
CML Outputs. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Unused Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Revision History . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Package Outline Drawing. . . . . . . . . . . . . . . . . . . . . . . . . . 41


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