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AM1808BZCEA3 bảng dữ liệu(PDF) 6 Page - Texas Instruments |
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AM1808BZCEA3 bảng dữ liệu(HTML) 6 Page - Texas Instruments |
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6 / 265 page  AM1808 SPRS653B – FEBRUARY 2010 – REVISED APRIL 2011 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. This data manual revision history highlights the changes made to the SPRS653A device-specific data manual to make it an SPRS653B revision. This device is now in the production data (PD) stage of development. Revision History See ADDITIONS/MODIFICATIONS/DELETIONS • Replaced CLKIN with OSCIN. Global • Removed EMA_A25. Section 2.5.1, Pin Map (Bottom View): Section 2.5 Pin Assignments • Updated pin names in Figure 2-1, Pin Map (Quad A), through Figure 2-4, Pin Map (Quad D). Table 2-1, Characteristics of the Device: Section 2 Device Overview • Corrected DDR2 max to 156 MHz and mDDR max to 150 MHz. Table 2-7, External Memory Interface A (EMIFA) Terminal Functions: • Corrected description for signal A18. Table 2-9, Serial Peripheral Interface (SPI) Terminal Functions: • Changed signal type to I/O for signal C16, C18, G17, and H17. Table 2-12, Enhanced Pulse Width Modulator (eHRPWM) Terminal Functions: • Changed signal type to Input for signal A4, C16, and D2. Section 2.7 Terminal Functions Table 2-14, Universal Asynchronous Receiver/Transmitter (UART) Terminal Functions: • Updated signal name for signal F4. Table 2-20, Ethernet Media Access Controller (EMAC) Terminal Functions: • Changed signal type to I/O for signal W18. Table 2-24, Universal Host-Port Interface (UHPI) Terminal Functions: • Changed signal type to Output for signal R16. Section 2.8 • Added new section. Unused Pin Configurations Section 4.1, Absolute Maximum Ratings Over Operating Junction Temperature Range (Unless Otherwise Noted): • Updated ESD Stress Voltage MAX values. Section 4.2, Recommended Operating Conditions: • Added DVDD18 under Supply Voltage. Section 4 Device Operating Condtions Section 4.3, Notes on Recommended Power-On Hours (POH), added. Section 4.4, Electrical Characteristics Over Recommended Ranges of Supply Voltage and Operating Junction Temperature (Unless Otherwise Noted): • Updated parameters for VOH and VOL. • Updated table notes 1 and 3. Section 5.3.1, Power-On Sequence: Section 5.3 Power Supplies • Changed VDDA_12_PLL0 to PLL0_VDDA, and VDDA_12_PLL1 to PLL1_VDDA in step 2b. Section 5.5 • Changed last sentence, first paragraph in description. Crystal Oscillator or External • Table 5-3, OSCIN Timing Requirements for an Externally Driven Clock, added table note. Clock Input Section 5.6.1, PLL Device-Specific Information: • Updated PLLn to PLL0 or PLL1, as appropriate in Figure 5-8, PLL External Filtering Components. • Added paragraph below figure. Section 5.6 • Updated OSCIN area to include DEEPSLEEP Enable in Figure 5-9, PLL Topology. Clock PLLs • Changed PLLREF MAX value in Table 5-4. Section 5.6.3, Dynamic Voltage and Frequency Scaling (DVFS): • Updated Maximum internal clock frequency specifications in Table 5-5. Section 5.7.1.4, AINTC System Interrupt Assignments: Section 5.7 Interrupts • Updated Interrupt Name and Source columns in Table 5-6. 6 Contents Copyright © 2010–2011, Texas Instruments Incorporated Submit Documentation Feedback Product Folder Link(s): AM1808 |
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