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MC74LVQ646DT bảng dữ liệu(PDF) 2 Page - Motorola, Inc |
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MC74LVQ646DT bảng dữ liệu(HTML) 2 Page - Motorola, Inc |
2 / 10 page LOGIC DIAGRAM C D Q OE DIR CBA SBA SAB CAB C D Q A0 B0 1 of 8 Channels To 7 Other Channels 1 3 21 22 2 23 MC74LVQ646 MOTOROLA LVQ DATA BR1478 2 FUNCTION TABLE Inputs Storage Registers Data Ports Operating Mode OE DIR CAB CBA SAB SBA QA QB An Bn Operating Mode H X Input Input ↑ ↑ X X NC NC X X Isolation, Hold Storage ↑ ↑ X X L H X X X X L H L H X X X X L H Store A and/or B Data L H Input Output ↑ X* L X NC NC NC NC L H L H Real Time A Data to B Bus H X NC NC X QA Stored A Data to B Bus ↑ X* L X L H NC NC L H L H Real Time A Data to B Bus; Store A Data H X L H NC NC L H QA QA Stored A Data to B Bus; Store A Data L L Output Input X* ↑ X L NC NC NC NC L H L H Real Time B Data to A Bus X H NC NC QB X Stored B Data to A Bus X* ↑ X L NC NC L H L H L H Real Time B Data to A Bus; Store B Data X H NC NC L H QB QB L H Stored B Data to A Bus; Store B Data H = High Voltage Level; L = Low Voltage Level; X = Don’t Care; ↑ = Low–to–High Clock Transition; ↑ = NOT Low–to–High Clock Transition; NC = No Change; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs. |
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