STK672-640A-E

No. A1130-5/21

Precautions

[GND wiring]

• To reduce noise on the 5V system, be sure to place the GND of C01 in the circuit given above as close as possible to

Pin 2 and Pin 6 of the hybrid IC. Also, to achieve accurate current settings, be sure to connect Vref GND to Pin 18

(S.G) used to set the current and to the point where P.G1 and P.G2 share a connection.

[Input pins]

• If VDD is being applied, use care that each input pin does not apply a negative voltage less than -0.3V to S.G, Pin 18,

and do not apply a voltage greater than or equal to VDD voltage.

• Do not wire by connecting the circuit pattern on the P.C.B side to Pins 7, 8, or 11 on the N.C. shown in the internal

block diagram.

• Apply 2.5V high level input to pins 10, 12, 13, 14, 15, and 17.

• Since the input pins do not have built-in pull-up resistors, when the open-collector type pins 10, 12, 13, 14, 15, and 17

are used as inputs, a 1 to 20k

Ω pull-up resistor (to VDD) must be used.

At this time, use a device for the open collector driver that has output current specifications that pull the voltage down

to less than 0.8V at Low level (less than 0.8V at Low level when IOL=5mA).

[Current setting Vref]

• Considering the specifications of the Vref input bias current, IIB, a value of 1kΩ or less is recommended for R02.

If the motor current is temporarily reduced, the circuit given below (STK672-630A-E: IOH>0.2A, STK672-640A-E:

IOH>0.3A) is recommended.

• Motor current peak value IOH setting

IOH=(Vref÷4.9) ÷Rs

The value of 4.9 in Equation above represents the Vref voltage as divided by a circuit inside the control IC.

Vref=(R02

÷ (R01+R02)) ×5V(or 3.3V)

Rs is an internal current detection resistor value of the hybrid IC.

Rs=0.141

Ω when using the STK672-630A-E

Rs=0.089

Ω when using the STK672-640A-E

5V

R01

R02

R3

5V

R01

R02

R3

Vref

Vref

IOH

0