Figure 2. Logic Diagram

C

D

Q

OEBA

OEAB

CBA

SBA

SAB

CAB

C

D

Q

A0

B0

1 of 8 Channels

To 7 Other Channels

1

3

21

22

2

23

MC74LCX652

MOTOROLA

LCX DATA

BR1339 — REV 3

2

FUNCTION TABLE

Inputs

Data Ports

Operating Mode

OEAB

OEBA

CAB

CBA

SAB

SBA

An

Bn

Operating Mode

L

H

Input

Input

↑

↑

X

X

X

X

Isolation, Hold Storage

↑

↑

X

X

l

h

l

h

Store A and/or B Data

H

H

Input

Output

↑

X*

L

X

L

H

L

H

Real Time A Data to B Bus

H

X

X

QA

Stored A Data to B Bus

↑

X*

L

X

l

h

L

H

Real Time A Data to B Bus; Store A Data

H

X

L

H

QA

QA

Clock A Data to B Bus; Store A Data

L

L

Output

Input

X*

↑

X

L

L

H

L

H

Real Time B Data to A Bus

X

H

QB

X

Stored B Data to A Bus

X*

↑

X

L

L

H

l

h

Real Time B Data to A Bus; Store B Data

X

H

QB

QB

L

H

Clock B Data to A Bus; Store B Data

H

L

Output

Output

↑

↑

H

H

QB

QA

Stored A Data to B Bus,

Stored B Data to A Bus

H = High Voltage Level; h = High Voltage Level One Setup Time Prior to the Low–to–High Clock Transition; L = Low Voltage Level; l = Low Voltage Level One Setup

Time Prior to the Low–to–High Clock Transition; X = Don’t Care;

↑ = Low–to–High Clock Transition; ↑ = NOT Low–to–High Clock Transition; QA = A input storage register;

QB = B input storage register; * = The clocks are not internally gated with either the Output Enables or the Source Inputs. Therefore, data at the A or B ports may be

clocked into the storage registers, at any time. For ICC reasons, Do Not Float Inputs.