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ADS8528SPM bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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ADS8528SPM bảng dữ liệu(HTML) 10 Page - Texas Instruments |
10 / 51 page ADS8528 ADS8548 ADS8568 SBAS543A – AUGUST 2011 – REVISED OCTOBER 2011 www.ti.com PARAMETER MEASUREMENT INFORMATION (continued) Table 1. Serial Interface Timing Requirements(1)(2) ADS8528, ADS8548, ADS8568 TEST PARAMETER CONDITION MIN TYP MAX UNIT CONVST_x high to XCLK rising edge tSCVX CLKSEL = 1 6 ns setup time ADS8528 66.67 ns tXCLK External conversion clock period ADS8548 72.46 ns ADS8568 85.11 ns ADS8528 1 15.0 MHz External conversion clock frequency ADS8548 1 13.8 MHz ADS8568 1 11.75 MHz External conversion clock duty cycle 40 60 % tCVL CONVST_x low time 20 ns tACQ Acquisition time 280 ns 19 20 tCCLK or tXCLK ADS8528, 1.33 μs CLKSEL = 0 tCONV Conversion time ADS8548, 1.45 μs CLKSEL = 0 ADS8568, 1.7 μs CLKSEL = 0 tDCVB CONVST_x high to BUSY high delay 25 ns tBUFS BUSY low to FS low time 0 ns ADS8528 0 ns Bus access finished to next conversion tFSCV ADS8548 20 ns start time ADS8568 40 ns tSCLK Serial clock period 0.022 10 μs Serial clock frequency 0.1 45 MHz Serial clock duty cycle 40 60 % tDMSB FS low to MSB valid delay 12 ns tHDO Output data to SCLK falling edge hold time 5 ns SCLK falling edge to new data valid tPDDO 17 ns propagation delay tDTRI FS high to SDO_x three-state delay 10 ns tSUDI Input data to SCLK falling edge setup time 3 ns tHDI Input data to SCLK falling edge hold time 5 ns (1) Over recommended operating free-air temperature range TA, AVDD = 5V, and DVDD = 2.7V to 5.5V, unless otherwise noted. (2) All input signals are specified with tR = tF = 1.5ns (10% to 90% of DVDD) and timed from a voltage level of (VIL + VIH)/2. 10 Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS8528 ADS8548 ADS8568 |
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