công cụ tìm kiếm bảng dữ liệu linh kiện điện tử |
|
GS7032-CVM bảng dữ liệu(PDF) 7 Page - Gennum Corporation |
|
GS7032-CVM bảng dữ liệu(HTML) 7 Page - Gennum Corporation |
7 / 9 page 14583 - 04 7 of 9 Fig. 6 Output Jitter vs. LBWC Fig. 7 Output Eye Diagram (270Mb/s) DETAILED DESCRIPTION The GS7032 Serializer is a bipolar integrated circuit used to convert parallel data into a serial format according to the SMPTE 259M-C standard. The device encodes both 8-bit and 10-bit TTL-compatible parallel signals producing serial data rates at 270Mb/s. It operates from a single 5V supply and is packaged in a 44 pin TQFP. Functional blocks within the device include the following: • input latches • sync detector • parallel to serial converter • SMPTE scrambler • NRZ to NRZI converter • internal cable driver • PLL for 10x parallel clock multiplication • lock detect The parallel data (PD0-PD9) and parallel clock (PCLKIN) are applied via pins 1 through 11 respectively. 1. SYNC DETECTOR The Sync Detector looks for the reserved words used in the TRS-ID sync word. The reserved words are 000-003 and 3FC-3FF in 10-bit hexadecimal, or 00 and FF in 8-bit hexadecimal. When the occurrence of either all zeros or all ones at inputs PD2-PD9 are detected, the lower two bits PD0 and PD1 are forced to zeros or ones, respectively. This makes the system compatible with 8-bit or 10-bit data. For non-SMPTE standard parallel data, the Sync Detector can be disabled with a logic input, Sync Detect Disable (pin 44). 2. SCRAMBLER The Scrambler is a linear feedback shift register used to pseudo-randomize the incoming serial data according to the fixed polynomial (X 9+X4+1). This minimizes the DC component in the output serial data stream. The NRZ to NRZI converter uses another polynomial (X+1) to convert a long sequence of ones to a series of transitions, minimizing polarity effects. These functions can be disabled by setting BYPASS high (pin 31). 3. PHASE LOCKED LOOP The PLL performs parallel clock multiplication and provides the timing signal for the serializer. It is composed of a phase/frequency detector (with no dead zone), charge pump, VCO, a divide-by-ten counter, and a divide by two counter. The phase/frequency detector allows a wider capture range and faster lock time than can be achieved with a phase discriminator alone. The discrimination of frequency also eliminates harmonic locking. With this type of discriminator, the PLL can be over-damped for good stability without sacrificing lock time. The charge pump delivers a 'charge packet' to the loop filter which is proportional to the system phase error. Internal voltage clamps are used to constrain the loop filter voltage between approximately 1.8 and 3.4 volts. The VCO is a differential low phase noise, factory trimmed design that provides increased immunity to PCB noise and precise control of the VCO centre frequency. The VCO has a pull range of ±15% about the centre frequency. The single external resistor, RVCO, sets the VCO frequency. GROUNDED FLOATING VCC 600 500 400 300 200 100 0 LOOP BANDWIDTH CONTROL (LBWC) (270Mb/s) |
Số phần tương tự - GS7032-CVM |
|
Mô tả tương tự - GS7032-CVM |
|
|
Link URL |
Chính sách bảo mật |
ALLDATASHEET.VN |
Cho đến nay ALLDATASHEET có giúp ích cho doanh nghiệp của bạn hay không? [ DONATE ] |
Alldatasheet là | Quảng cáo | Liên lạc với chúng tôi | Chính sách bảo mật | Trao đổi link | Tìm kiếm theo nhà sản xuất All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |