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GS1582 bảng dữ liệu(PDF) 11 Page - Gennum Corporation |
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GS1582 bảng dữ liệu(HTML) 11 Page - Gennum Corporation |
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11 / 115 page  GS1582 Multi-Rate Serializer with Cable Driver, Audio Multiplexer and ClockCleanerTM Data Sheet 40117 - 3 March 2009 11 of 115 A3 F/DE Synchronous with PCLK Input PARALLEL DATA TIMING Signal levels are LVCMOS/LVTTL compatible. TIM_861 = LOW: Used to indicate the ODD / EVEN field of the video signal when DETECT_TRS is set LOW. The device will set the F bit in all outgoing TRS signals for the entire period that the F input signal is HIGH (IOPROC_EN/DIS must also be HIGH). The F signal should be set HIGH for the entire period of field 2 and should be set LOW for all lines in field 1 and for all lines in progressive scan systems. The F signal is ignored when DETECT_TRS = HIGH. TIM_861 = HIGH: The DE signal is used to indicate the active video period. DE is HIGH for active data and LOW for blanking. See Section 4.3.1 and Section 4.3.2 for timing details. The DE signal is ignored when DETECT_TRS = HIGH. A4 H/HSYNC Synchronous with PCLK Input PARALLEL DATA TIMING Signal levels are LVCMOS/LVTTL compatible. TIM_861 = LOW: The H signal is used to indicate the portion of the video line containing active video data, when DETECT_TRS is set low. Active Line Blanking The H signal should be set HIGH for the entire horizontal blanking period, including the EAV and SAV TRS words, and LOW otherwise. This is the default setting. TRS Based Blanking (H_CONFIG = 1h) The H signal should be set HIGH for the entire horizontal blanking period as indicated by the H bit in the received TRS ID words, and LOW otherwise. The H signal is ignored when DETECT_TRS = HIGH. TIM_861 = HIGH: The HSYNC signal indicates horizontal timing. See Section 4.3.1 for timing details. The HSYNC signal is ignored when DETECT_TRS = HIGH. A5, E1, G10, K8 CORE_VDD Non Synchronous Input Power Power supply connection for the digital core logic. Connect to +1.8V DC digital. A6, B6 PD_VDD Analog Input Power Power supply connection for the phase detector. Connect to +1.8V DC analog. A7 LF Analog Input PLL loop filter connection. A8 VCO_VCC Analog Output Power Power supply for the external voltage controlled oscillator. 2.5V DC supplied by the device to the external VCO. A9 VCO Analog Input Input from external VCO. A10 CP_VDD Analog Input Power Power supply connection for the charge pump and on chip VCO regulator. Connect to +3.3V DC analog. Table 1-1: Pin Descriptions (Continued) Pin Number Name Timing Type Description |
Số phần tương tự - GS1582_09 |
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Mô tả tương tự - GS1582_09 |
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