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10 / 20 page GENNUM CORPORATION 522 - 26 - 03 10 of 20 pump drops with reducing data transitions. During pathological signals, the data transition density reduces from 0.5 to 0.05 but the slew PLL’s performance does not change significantly. Because most of the PLL circuitry is digital, it is very robust as digital systems are generally more robust than their analog counterparts. Signals which represent the internal functionality, like DM (86), can be generated without adding additional artifacts. Thus, system debugging is possible with these features. The complete slew PLL is made up of several blocks including the phase detector, the charge pump and an external Voltage Controlled Oscillator (VCO) which are described in the following sections. Phase lock loop frequency synthesis and lock logic are also described. Fig. 14 PLL Characteristics 5.1. Phase Detector The phase detector portion of the slew PLL used in the GS1522 is a bi-level digital phase detector. It indicates whether the data transition occurred before or after with respect to the falling edge of the internal clock. When the phase detector is locked, the data transition edges are aligned to the falling edge of the clock. The input data is then sampled by the rising edge of the clock, as shown in Figure 15. In this manner, the allowed input jitter is 1UI p-p in an ideal situation. However, due to setup and hold time, the GS1522 typically achieves 0.8UI p-p input jitter tolerance without causing any errors in this block. When the signal is locked to the internal clock, the control output from the phase detector is refreshed at the transition of each rising edge of the data input. During this time, the phase of the clock drifts in one direction. Fig. 15 Phase Detector Characteristics During pathological signals, the amount of jitter that the phase detector will add can be calculated. By choosing the proper loop bandwidth, the amount of phase detector induced jitter can also be limited. Typically, for a 1.41MHz loop bandwidth at 0.2UI input jitter modulation, the phase detector induced jitter is about 0.015UIp-p. This is not significant, even in the presence of pathological signals. 5.2. Charge Pump The charge pump in a slew PLL is different from the charge pump in a linear PLL. There are two main functions of the charge pump: to hold the frequency information of the input data and to provide a binary control voltage to the VCO. The charge pump holds the frequency information of the input data. This information is held by CCP1 which is connected between LFS (82) and LFS (84). CCP2, which is connected between LFS and LFA_VEE (89), is used to remove common mode noise. Both CCP1 and CCP2 should have the same value. The charge pump provides a binary control voltage to the VCO depending upon the phase detector output. The output pin LFA (90) controls the VCO. Internally there is a 500 Ω pull-up resistor which is driven with a 100µA current called Ι P. Another analog current Ι F, with 5mA maximum drive proportional to the voltage across the CCP1, is applied at the same node. The voltage at the LFA node is VLFA_VCC - 500(ΙP+ΙF) at any time. Because of the integrator, Ι F changes very slowly whereas Ι P can change at the positive edge of the data transition as often as a clock period. In the locked position, the average voltage at LFA (VLFA_VCC – 500(ΙP/2+ΙF) is such that VCO generates frequency ƒ equal to the data rate clock frequency. Since Ι P is changing all the time between 0A and 100µA, there are two levels generated at the LFA output. 5.3. VCO The GO1515 is an external hybrid VCO which has a centre frequency of 1.485GHz. It is guaranteed to provide 1.485/1.001GHz within the control voltage (3.1V – 4.65V) of the GS1522 over process, power supply and temperature. 0.2 0.1 0.0 INPUT OUTPUT SLEW PLL RESPONSE 0.2 0.1 0.0 INPUT OUTPUT LINEAR (CONVENTIONAL) PLL RESPONSE IN-PHASE CLOCK INPUT CLOCK WITH JITTER OUTPUT DATA 0.8UI RE-TIMING EDGE PHASE ALIGNMENT EDGE |
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