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8 / 98 page DAC1008D650 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2010. All rights reserved. Product data sheet Rev. 2 — 17 December 2010 8 of 98 NXP Semiconductors DAC1008D650 2 ×, 4× or 8× interpolating DAC with JESD204A Vidth input differential threshold voltage |V gpd| < 50 mV [4] C −100 - +100 mV Ri input resistance D - 10 - M Ω CI input capacitance D - 0.5 - pF Digital inputs (SDO, SDIO, SCLK, SCS_N, RESET_N) VIL LOW-level input voltage CGND - 0.3VDDD V VIH HIGH-level input voltage C0.7VDDD -VDDD V IIL LOW-level input current VIL =0.3VDDD VI - 1 - μA IIH HIGH-level input current VIH =0.7VDDD VI - 1 - μA Digital outputs (SDO, SDIO) VOL LOW-level output voltage Iload =2mA C GND - 0.13 V VOH HIGH-level output voltage Iload =2mA C 1.65 - VDDD V Digital inputs (Vin_p/Vin_n)[5] VI(cm) common-mode input voltage D - 0.78 - V VI(dif)(p-p) peak-to-peak differential input voltage D 175 - 1000 mV Ztt Vtt source impedance D - 0.7 - Ω ΔZ i differential input impedance D - 100 - Ω Digital outputs (SYNC_OUTN/SYNC_OUTP)[6] Vo(cm) common-mode output voltage C- 1.18 - V Vo(dif)(p-p) peak-to-peak differential output voltage C- 0.45 - V Digital inputs/outputs (MDS_N/MDS_P) Vo(dif)(p-p) peak-to-peak differential output voltage D - 600 - mV Co(L) Output load capacitance between pins GND and MDS_N or MDS_P D- - 10 pF CI Input capacitance between pins GND and MDS_N or MDS_P D - 0.3 - pF Table 5. Characteristics …continued VDDA(1V8) =VDDD = 1.7 V to 1.9 V; VDDA(3V3) = 3.13 V to 3.47 V; AGND and GND are shorted together; Tamb = −40 °C to +85 °C; typical values measured at V DDA(1V8) =VDDD =1.8 V; VDDA(3V3) =3.3 V; Tamb =+25 °C; RL =50 Ω; IO(fs) =20mA; maximum sample rate; PLL off unless otherwise specified. Symbol Parameter Conditions Test[1] Min Typ Max Unit |
Số phần tương tự - DAC1008D650_1012 |
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Mô tả tương tự - DAC1008D650_1012 |
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