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74LVC1G00
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 8 — 20 October 2010
7 of 17
NXP Semiconductors
74LVC1G00
Single 2-input NAND gate
Table 9.
Measurement points
Supply voltage
Input
Output
VCC
VM
VM
1.65 V to 1.95 V
0.5VCC
0.5VCC
2.3 V to 2.7 V
0.5VCC
0.5VCC
2.7V
1.5V
1.5V
3.0V to 3.6V
1.5V
1.5V
4.5 V to 5.5 V
0.5VCC
0.5VCC
Test data is given in Table 10.
Definitions for test circuit:
RL = Load resistance.
CL = Load capacitance including jig and probe capacitance.
RT = Termination resistance should be equal to the output impedance Zo of the pulse generator.
VEXT = External voltage for measuring switching times.
Fig 8.
Test circuit for measuring switching times
VEXT
VCC
VI
VO
mna616
DUT
CL
RT
RL
RL
G
Table 10.
Test data
Supply voltage
Input
Load
VEXT
VCC
VI
tr =tf
CL
RL
tPLH, tPHL
1.65 V to 1.95 V
VCC
≤ 2.0ns
30pF
1 k
Ω
open
2.3 V to 2.7 V
VCC
≤ 2.0ns
30pF
500
Ω
open
2.7V
2.7V
≤ 2.5ns
50pF
500
Ω
open
3.0V to 3.6V
2.7V
≤ 2.5ns
50pF
500
Ω
open
4.5 V to 5.5 V
VCC
≤ 2.5ns
50pF
500
Ω
open


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