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ADS41B29IRGZT bảng dữ liệu(PDF) 9 Page - Texas Instruments

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ADS41B29
ADS41B49
www.ti.com
SBAS486D – NOVEMBER 2009 – REVISED DECEMBER 2010
ADS41B49, ADS41B29 Pin Descriptions (LVDS Mode) (continued)
# OF
PIN NAME
PIN NUMBER
PINS
FUNCTION
DESCRIPTION
This pin functions as a serial interface enable input when RESET is low. When
SEN
27
1
I
RESET is high, SEN has no function and should be tied to AVDD. This pin has an
internal 180k
Ω pull-up resistor to AVDD.
Output buffer enable input, active high; this pin has an internal 100k
Ω pull-up
OE
7
1
I
resistor to DRVDD.
Data format select input. This pin sets the DATA FORMAT (twos complement or
DFS
6
1
I
offset binary) and the LVDS/CMOS output interface type.
RESERVED
23
1
I
Digital control pin, reserved for future use
CLKOUTP
5
1
O
Differential output clock, true
CLKOUTM
4
1
O
Differential output clock, complement
D0_D1_P
Refer to Figure 1
1
O
Differential output data D0 and D1 multiplexed, true
D0_D1_M
Refer to Figure 1
1
O
Differential output data D0 and D1 multiplexed, complement
D2_D3_P
Refer to Figure 1
1
O
Differential output data D2 and D3 multiplexed, true
D2_D3_M
Refer to Figure 1
1
O
Differential output data D2 and D3 multiplexed, complement
D4_D5_P
Refer to Figure 1
1
O
Differential output data D4 and D5 multiplexed, true
D4_D5_M
Refer to Figure 1
1
O
Differential output data D4 and D5 multiplexed, complement
D6_D7_P
Refer to Figure 1
1
O
Differential output data D6 and D7 multiplexed, true
D6_D7_M
Refer to Figure 1
1
O
Differential output data D6 and D7 multiplexed, complement
D8_D9_P
Refer to Figure 1
1
O
Differential output data D8 and D9 multiplexed, true
D8_D9_M
Refer to Figure 1
1
O
Differential output data D8 and D9 multiplexed, complement
D10_D11_P
Refer to Figure 1
1
O
Differential output data D10 and D11 multiplexed, true
D10_D11_M
Refer to Figure 1
1
O
Differential output data D10 and D11 multiplexed, complement
D12_D13_P
Refer to Figure 1
1
O
Differential output data D12 and D13 multiplexed, true
D12_D13_M
Refer to Figure 1
1
O
Differential output data D12 and D13 multiplexed, complement
This pin functions as an out-of-range indicator after reset, when register bit
OVR_SDOUT
3
1
O
READOUT = 0, and functions as a serial register readout pin when
READOUT = 1. This pin is a 1.8V CMOS output pin (running off of DRVDD).
DRVDD
2, 35
2
I
1.8V digital and output buffer supply
DRGND
1, 36, PAD
2
I
Digital and output buffer ground
NC
Refer to Figure 1
Do not connect
Copyright © 2009–2010, Texas Instruments Incorporated
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