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2 / 11 page CS1501 2 DS927PP6 1. INTRODUCTION Figure 1. CS1501 Block Diagram The CS1501 digital power factor correction (PFC) control IC is designed to deliver the lowest system cost by reducing the total number of system components and optimizing the EMI noise signature, which reduces the conducted EMI filter requirements. The CS1501 digital algorithm determines the behavior of the boost converter during startup, normal operation, and under fault conditions (overvoltage, overcurrent, and overtemperature). Figure 1 illustrates a high-level block diagram of the CS1501. The PFC processor logic regulates the power transfer by using an adaptive digital algorithm to optimize the PFC active-switch (MOSFET) drive signal duty cycle and switching frequency. The adaptive controller uses independent analog-to-digital converter (ADC) channels when sensing the feedback and feedforward analog signals required to implement the digital PFC control algorithm. The AC mains rectified voltage (on pin IAC) and PFC output link voltage (on pin IFB) are transformed by the PFC processor logic and used to generate the optimum PFC active-switch drive signal (GD) by calculating the optimal switching frequency and tON time on a cycle-by-cycle basis. An auxiliary winding is typically added to the PFC boost inductor to provide zero-current detection (ZCD) information. The ZCD acts as a demagnetization sensor used to monitor the PFC active-switching behavior and efficiency. The auxiliary voltage is normalized using an external attenuator and is connected to the ZCD pin, providing the CS1501 a mechanism to detect the valley/zero crossings. The ZCD comparator looks for the zero crossing on the auxiliary winding and switches when the auxiliary voltage is below zero. Switching in the valley of the oscillation minimizes the switching losses and reduces EMI noise. The PFC controller uses a current sensor for overcurrent protection. The boost inductor peak current is measured across an external resistor in the switching circuit on a cycle-by-cycle basis. An overcurrent fault is generated when the sense voltage applied to the CS pin exceeds a predefined reference voltage. The CS1501 includes a supervisor & protection circuit to manage startup, shutdown, and fault conditions. The protection circuit is designed to prevent output overvoltage as a result of load and AC mains transients. The PFC power converter main rectified voltage (Vrect) and output link voltage (Vlink) are monitored for overvoltage faults which would lead to shutdown of the PFC controller. The PFC overvoltage protection is designed for auto-recovery, i.e. operation resumes once the fault clears. V Z POR + - VDD(on) VDD(off) Voltage Regulator 8 VDD 5 ZCD + - VZCD(th) 7 GD Zero Crossing Detect 6 GND IFB IAC VDD tLEB VDD 15k 24k 3 VDD 15k 24k 1 ADC ADC tZCB 4 CS 600 + - CS Threshold + - CS Clamp VCS(clamp) VCS(th) STBY VDD 600k 2 Iref Iref |
Số phần tương tự - CS1501-FSZ |
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Mô tả tương tự - CS1501-FSZ |
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