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STK14C88-C45I bảng dữ liệu(PDF) 7 Page - Cypress Semiconductor |
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STK14C88-C45I bảng dữ liệu(HTML) 7 Page - Cypress Semiconductor |
7 / 20 page STK14C88 Document Number: 001-52038 Rev. *C Page 7 of 20 SRAM Write Cycle #1 and #2 (VCC = 5.0V ± 10%)[4] NO. Symbols Parameter STK14C88-25 STK14C88-35 STK14C88-45 Unit Min Max Min Max Min Max #1 #2 Alt. 12 tAVAV tAVAV tWC Write Cycle Time 25 – 35 – 45 – ns 13 tWLWH tWLEH tWP Write Pulse Width 20 – 25 – 30 – ns 14 tELWH tELEH tCW Chip Enable to End of Write 20 – 25 – 30 – ns 15 tDVWH tDVEH tDW Data Setup to End of Write 10 – 12 – 15 – ns 16 tWHDX tEHDX tDH Data Hold after End of Write 0 – 0 – 0 – ns 17 tAVWH tAVEH tAW Address Setup to End of Write 20 – 25 – 30 – ns 18 tAVWL tAVEL tAS Address Setup to Start of Write 0 – 0 – 0 – ns 19 tWHAX tEHAX tWR Address Hold after End of Write 0 – 0 – 0 – ns 20 tWLQZ [8, 9] tWZ Write Enable to Output Disable – 10 – 13 – 15 ns 21 tWHQX tOW Output Active after End of Write 5 – 5 – 5 – ns Figure 6. SRAM Write Cycle 1: W Controlled [10, 11] Figure 7. SRAM Write Cycle 2: E Controlled [10, 11] DATA OUT E ADDRESS W DATA IN PREVIOUS DATA 12 tAVAV 13 tWHDX 19 tWHAX 13 tWLWH 18 tAVWL 17 tAVWH DATA VALID 20 tWLQZ 15 tDVWH HIGH IMPEDANCE 21 tWHQX 14 tELWH 12 tAVAV 16 tEHDX 13 tWLEH 19 tEHAX 18 tAVEL 17 tAVEH DATA VALID 15 tDVEH HIGH IMPEDANCE 14 tELEH DATA OUT E ADDRESS W DATA IN Notes 9. If W is low when E goes low, the outputs remain in the high impedance state. 10. E or W must be VIH during address transitions. 11. HSB must be high during SRAM write cycles. [+] Feedback |
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