STK14C88-3

Document Number: 001-50592 Rev. *D

Page 11 of 18

Table 3. SRAM Write Cycle

Parameter

Description

35 ns

45 ns

Unit

Min

Max

Min

Max

Cypress

Parameter

Alt

Write Cycle Time

35

45

ns

Write Pulse Width

25

30

ns

Chip Enable To End of Write

25

30

ns

Data Setup to End of Write

12

15

ns

Data Hold After End of Write

0

0

ns

Address Setup to End of Write

25

30

ns

Address Setup to Start of Write

0

0

ns

Address Hold After End of Write

0

0

ns

Write Enable to Output Disable

13

15

ns

Output Active After End of Write

5

5

ns

Switching Waveforms

Figure 9. SRAM Write Cycle 1: WE Controlled [13, 14]

Figure 10. SRAM Write Cycle 2: CE Controlled [13, 14]

ADDRESS

CE

WE

DATA IN

DATA OUT

DATA VALID

HIGH IMPEDANCE

PREVIOUS DATA

ADDRESS

CE

WE

DATA IN

DATA OUT

HIGH IMPEDANCE

DATA VALID

Notes

12. If WE is Low when CE goes Low, the outputs remain in the high impedance state.

14. HSB must be HIGH during SRAM WRITE cycles.

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