65nm CMOS Standard Cell

FUJITSU MICROELECTRONICS AMERICA, INC.

Corporate Headquarters

1250 E. Arques Avenue, M/S 333, Sunnyvale, CA 94085-5401

Tel: (800) 866-8608 Fax: (408) 737-5999

E-mail: inquiry@fma.fujitsu.com Web Site: http://us.fujitsu.com/micro

© 2008 Fujitsu Microelectronics America, Inc.

All company and product names are trademarks or

registered trademarks of their respective owners.

Printed in the U.S.A. SMS-FS-21293-3/2008

Memory Macros and Compilers

•1 RW SRAM in 16K X 40-bit Max. Configuration

•2 RW SRAM in 4K X 18-bit Max. Configuration

Phase-Lock Loops

• Analog: up to 3.2Ghz

• DLL

I/O: High Speed Interface and Conventional IOs

• 2.5V and 3.3V LVCMOS

• P-CML, LVDS, SSTL, HSTL

• PCI Express, S-ATA, DDR, USB, DDR, HDMI, CDR

• 3.125Gbps XAUI, SFI, SPI

Mix-Signal Macros

ADC

DAC

• 8-bit 54MS/s

• 8-bit 300kS/s

• 8-bit 110MS/s

• 8-bit 1MS/s

• 10-bit 1MS/s

• 10-bit 300kS/s

• 10-bit 33MS/s

• 10-bit 1MS/s

• 10-bit 1110MS/s

• 10-bit 40MS/s

• 12-bit 80MS/s Dual

• 10-bit 54MS/s

• 10-bit 110MS/s

SoC IP Cores

Networking and Communication

• PCI-Express Link & PHY, S-ATA Link & PHY, SPI4,

10/100/1000 Ethernet

Processors and DSP

• ARM7, 9, 11, ARC, Tensilica

Std. Bus Controllers & Bus Bridges

• USB2.0 Device/Host Controller & PHY, PCI controller,

SD/CF Card IF, I2C, UART

Multimedia Access

• HDMI Link & PHY, JPEG, NTSC/PAL, DES/AES Encryption

Memory Controllers

• Mobile DDR, DDR2/3, FCRAM, SDRAM

Specifications

Analog

SRAM

LOGIC

I/O

6.3mm

I/O

Peripheral

Peripheral

CORE

• Logic: 4Mgate (Usage ratio 60%)

• Macro: 2Mgate (SRAM: 0.5M-bit, PLL etc.)

65nm compared to 90nm of the same design

60% area

reduction

4.9mm

Analog

SRAM

LOGIC