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ADS4222IRGCT bảng dữ liệu(PDF) 10 Page - Texas Instruments |
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ADS4222IRGCT bảng dữ liệu(HTML) 10 Page - Texas Instruments |
10 / 104 page DAn_P DBn_P DAn_M DBn_M GND Logic0 V (1) ODL = 350mV - Logic1 V (1) ODH =+350mV V OCM ADS4222, ADS4225, ADS4226 ADS4242, ADS4245, ADS4246 SBAS533C – MARCH 2011 – REVISED JUNE 2011 www.ti.com DIGITAL CHARACTERISTICS At AVDD = 1.8V and DRVDD = 1.8V, unless otherwise noted. DC specifications refer to the condition where the digital outputs do not switch, but are permanently at a valid logic level '0' or '1'. ADS424x/422x PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DIGITAL INPUTS (RESET, SCLK, SDATA, SEN, CTRL1, CTRL2, CTRL3)(1) High-level input voltage 1.3 V All digital inputs support 1.8V and 3.3V CMOS logic levels Low-level input voltage 0.4 V SDATA, SCLK(2) VHIGH = 1.8V 10 µA High-level input current SEN(3) VHIGH = 1.8V 0 µA SDATA, SCLK VLOW = 0V 0 µA Low-level input current SEN VLOW = 0V 10 µA DIGITAL OUTPUTS, CMOS INTERFACE (DA[13:0], DB[13:0], CLKOUT, SDOUT) High-level output voltage DRVDD – 0.1 DRVDD V Low-level output voltage 0 0.1 V Output capacitance (internal to device) pF DIGITAL OUTPUTS, LVDS INTERFACE High-level output With an external VODH 270 350 430 mV differential voltage 100 Ω termination Low-level output With an external VODL –430 –350 –270 mV differential voltage 100 Ω termination Output common-mode voltage VOCM 0.9 1.05 1.25 V (1) SCLK, SDATA, and SEN function as digital input pins in serial configuration mode. (2) SDATA, SCLK have internal 150k Ω pull-down resistor. (3) SEN has an internal 150k Ω pull-up resistor to AVDD. Because the pull-up is weak, SEN can also be driven by 1.8V or 3.3V CMOS buffers. (1) With external 100 Ω termination. Figure 1. LVDS Output Voltage Levels 10 Submit Documentation Feedback Copyright © 2011, Texas Instruments Incorporated Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246 |
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