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TC1796 bảng dữ liệu(PDF) 7 Page - Infineon Technologies AG |
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TC1796 bảng dữ liệu(HTML) 7 Page - Infineon Technologies AG |
7 / 134 page TC1796 Summary of Features Data Sheet 7 V1.0, 2008-04 1 Summary of Features • High-performance 32-bit super-scalar TriCore V1.3 CPU with 4-stage pipeline – Superior real-time performance – Strong bit handling – Fully integrated DSP capabilities – Single precision Floating Point Unit (FPU) – 150 MHz operation at full temperature range • 32-bit Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) • Multiple on-chip memories – 2 Mbyte Program Flash Memory (PFLASH) with ECC – 128 Kbyte Data Flash Memory (DFLASH) usable for EEPROM emulation – 136 Kbyte Data Memory (LDRAM, SRAM, SBRAM) – 8 Kbyte Dual-Ported Memory (DPRAM) – 48 Kbyte Code Scratchpad Memory (SPRAM) – 16 Kbyte Instruction Cache (ICACHE) – 16 Kbyte BootROM (BROM) • 16-Channel DMA Controller • 32-bit External Bus Interface Unit (EBU) with – 75 dedicated address/data bus, clock, and control lines – Synchronous burst Flash access capability • Sophisticated interrupt system with 2 × 255 hardware priority arbitration levels serviced by CPU or PCP2 • High performing on-chip bus structure – Two 64-bit Local Memory Buses between EBU, Flash and Data Memory – 32-bit System Peripheral Bus (SPB) for on-chip peripheral and functional units – 32-bit Remote Peripheral Bus (RPB) for high-speed on-chip peripheral units – Two bus bridges (LFI Bridge, DMA Controller) • Peripheral Control Processor with single cycle instruction (PCP2) – 16 Kbyte Parameter Memory (PRAM) – 32 Kbyte Code Memory (CMEM) • Versatile On-chip Peripheral Units – Two Asynchronous/Synchronous Serial Channels (ASC) with baud rate generator, parity, framing and overrun error detection – Two High-Speed Synchronous Serial Channels (SSC) with programmable data length and shift direction – Two serial Micro Second Bus interfaces (MSC) for serial port expansion to external power devices – Two High-Speed Micro Link interfaces (MLI) for serial inter-processor communication |
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