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ADRF6702 bảng dữ liệu(PDF) 2 Page - Analog Devices |
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ADRF6702 bảng dữ liệu(HTML) 2 Page - Analog Devices |
2 / 36 page ADRF6702 Rev. 0 | Page 2 of 36 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 General Description ......................................................................... 1 Functional Block Diagram .............................................................. 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Timing Characteristics ................................................................ 6 Absolute Maximum Ratings............................................................ 7 ESD Caution.................................................................................. 7 Pin Configuration and Function Descriptions............................. 8 Typical Performance Characteristics ........................................... 10 Theory of Operation ...................................................................... 15 PLL + VCO.................................................................................. 15 Basic Connections for Operation............................................. 15 External LO ................................................................................. 15 Loop Filter ................................................................................... 16 DAC-to-IQ Modulator Interfacing .......................................... 17 Adding a Swing-Limiting Resistor ........................................... 17 IQ Filtering .................................................................................. 18 Baseband Bandwidth ................................................................. 18 Device Programming and Register Sequencing..................... 18 Register Summary .......................................................................... 19 Register Description....................................................................... 20 Register 0—Integer Divide Control (Default: 0x0001C0) .... 20 Register 1—Modulus Divide Control (Default: 0x003001).. 21 Register 2—Fractional Divide Control (Default: 0x001802) 21 Register 3—Σ-Δ Modulator Dither Control (Default: 0x10000B).................................................................................... 22 Register 4—PLL Charge Pump, PFD, and Reference Path Control (Default: 0x0AA7E4)................................................... 23 Register 5—LO Path and Modulator Control (Default: 0x0000D5) ................................................................................... 25 Register 6—VCO Control and VCO Enable (Default: 0x1E2106).................................................................................... 26 Register 7—External VCO Enable ........................................... 26 Characterization Setups................................................................. 27 Evaluation Board ............................................................................ 29 Evaluation Board Control Software......................................... 29 Outline Dimensions ....................................................................... 34 Ordering Guide .......................................................................... 34 REVISION HISTORY 4/11—Revision 0: Initial Version |
Số phần tương tự - ADRF6702 |
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Mô tả tương tự - ADRF6702 |
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