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MCF51QM128 bảng dữ liệu(PDF) 39 Page - Freescale Semiconductor, Inc |
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MCF51QM128 bảng dữ liệu(HTML) 39 Page - Freescale Semiconductor, Inc |
39 / 69 page Figure TBD Figure 10. Typical TUE vs. ADC conversion rate 12-bit single-ended mode Figure TBD Figure 11. Typical ENOB vs. Averaging for 16-bit differential and 16-bit single-ended modes 6.6.2 CMP and 6-bit DAC electrical specifications Table 25. Comparator and 6-bit DAC electrical specifications Symbol Description Min. Typ. Max. Unit VDD Supply voltage 1.71 — 3.6 V IDDHS Supply current, High-speed mode (EN=1, PMODE=1) — — 200 μA IDDLS Supply current, low-speed mode (EN=1, PMODE=0) — — 20 μA VAIN Analog input voltage VSS – 0.3 — VDD V VAIO Analog input offset voltage — — 20 mV VH Analog comparator hysteresis1 • CR0[HYSTCTR] = 00 • CR0[HYSTCTR] = 01 • CR0[HYSTCTR] = 10 • CR0[HYSTCTR] = 11 — — — — 5 10 20 30 — — — — mV mV mV mV VCMPOh Output high VDD – 0.5 — — V VCMPOl Output low — — 0.5 V tDHS Propagation delay, high-speed mode (EN=1, PMODE=1) 20 50 200 ns tDLS Propagation delay, low-speed mode (EN=1, PMODE=0) 120 250 600 ns Analog comparator initialization delay2 — — 40 μs IDAC6b 6-bit DAC current adder (enabled) — 7 — μA INL 6-bit DAC integral non-linearity –0.5 — 0.5 LSB3 DNL 6-bit DAC differential non-linearity –0.3 — 0.3 LSB 1. Typical hysteresis is measured with input voltage range limited to 0.6 to VDD-0.6V. 2. Comparator initialization delay is defined as the time between software writes to change control inputs (Writes to DACEN, VRSEL, PSEL, MSEL, VOSEL) and the comparator output settling to a stable level. 3. 1 LSB = Vreference/64 Analog MCF51QM128 Advance Information Data Sheet, Rev. 2, 05/2011. Freescale Semiconductor, Inc. Preliminary 39 |
Số phần tương tự - MCF51QM128 |
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Mô tả tương tự - MCF51QM128 |
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