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ISL24211 bảng dữ liệu(PDF) 9 Page - Intersil Corporation

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nhà sản xuất  INTERSIL [Intersil Corporation]
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ISL24211
9
FN7585.0
February 23, 2011
ISL24211 Programming
The ISL24211 accepts I2C bus address and data when the WP
pin is high. The ISL24211 ignores the I2C bus when the WP pin is
low. Figure 10 shows the serial data format for writing the
register and programming the EEPROM. Figure 11 shows the
serial data format for reading the DAC register. Table 2 shows the
truth table for reading and writing the device.
Programming the EEPROM memory transfers the current DAC
register value to the EEPROM and occurs when the control bits
select the programming mode and the AVDD voltage is >10.8V.
After the EEPROM programming cycle is started, the WP pin can
be returned to logic low while the EEPROM write completes,
which takes a maximum of 100ms.
The ISL24211 uses a 6-bit I2C address, which is “100111yx” for
the first transmitted byte. Bit x is the R/W bit, and Bit y is the LSB
(D0) of the DCP register code to be written. The complete read
and write protocol is shown in Figures 10 and 11.
I2C Bus Signals
The ISL24211 uses fixed voltages for its I2C thresholds, rather
than the percentage of VDD described in the I2C specification
(see Table 3). This should not cause a problem in most systems,
but the I2C logic levels in a specific design should be checked to
ensure they are compatible with the ISL24211.
FIGURE 9. EEPROM PROGRAMMING FLOWCHART
Erase Pulse
Start EEPROM
Programming
Are EEPROM
Cells Erased?
No
Yes
Write Pulse
Are
EEPROM Cells
Programmed?
EEPROM
Programming
Complete
No
Yes
TABLE 2. ISL24211 READ AND WRITE CONTROL
WP PIN
R/W
P
FUNCTION
0
1
X
Read Register.
0
0
1
Will acknowledge I2C
transactions. Will not write to
register.
0
0
0
Will acknowledge I2C
transactions. Will not write to
EEPROM.
1
1
X
Read DAC Register.
10
1
Write DAC Register.
10
0
Program EEPROM.
TABLE 3. ISL24211 I2C BUS LOGIC LEVELS
SYMBOL
ISL24211
I2C STANDARD
VIL_I2C
0.55V
0.3*VDD
VIH_I2C
1.44V
0.7*VDD


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