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ADS4226IRGC25 bảng dữ liệu(PDF) 11 Page - Texas Instruments |
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11 / 97 page ADS4222, ADS4225, ADS4226 ADS4242, ADS4245, ADS4246 www.ti.com SBAS533 – MARCH 2011 Pin Descriptions (LVDS Mode) (continued) PIN NAME PIN NUMBER # OF PINS FUNCTION DESCRIPTION Serial interface RESET input. When using the serial interface mode, the internal registers must be initialized through a hardware RESET by applying a high pulse on this pin or by using the RESET 12 1 Input software reset option; refer to the Serial Interface Configuration section. In parallel interface mode, the RESET pin must be permanently tied high. SCLK and SEN are used as parallel control pins in this mode. This pin has an internal 150k Ω pull-down resistor. This pin functions as a serial interface clock input when RESET is low. It controls SCLK 13 1 Input the low-speed mode selection when RESET is tied high; see Table 5 for detailed information. This pin has an internal 150k Ω pull-down resistor. SDATA 14 1 Input Serial interface data input; this pin has an internal 150k Ω pull-down resistor. This pin functions as a serial interface enable input when RESET is low. It controls the output interface and data format selection when RESET is tied high; SEN 15 1 Input see Table 6 for detailed information. This pin has an internal 150k Ω pull-up resistor to AVDD. This pin functions as a serial interface register readout when the READOUT bit is SDOUT 64 1 Output enabled. When READOUT = 0, this pin forces a logic low and is not put in 3-state. CTRL1 35 1 Input Digital control input pins. Together, they control the various power-down modes. CTRL2 36 1 Input Digital control input pins. Together, they control the various power-down modes. CTRL3 37 1 Input Digital control input pins. Together, they control the various power-down modes. CLKOUTP 57 1 Output Differential output clock, true CLKOUTM 56 1 Output Differential output clock, complement Refer to Figure 2 and DA0P, DA0M 2 Output Channel A differential output data pair, D0 and D1 multiplexed Figure 3 Refer to Figure 2 and DA2P, DA2M 2 Output Channel A differential output data D2 and D3 multiplexed Figure 3 Refer to Figure 2 and DA4P, DA4M 2 Output Channel A differential output data D4 and D5 multiplexed Figure 3 Refer to Figure 2 and DA6P, DA6M 2 Output Channel A differential output data D6 and D7 multiplexed Figure 3 Refer to Figure 2 and DA8P, DA8M 2 Output Channel A differential output data D8 and D9 multiplexed Figure 3 DA10P, Refer to Figure 2 and 2 Output Channel A differential output data D10 and D11 multiplexed DA10M Figure 3 DA12P, Refer to Figure 3 2 Output Channel A differential output data D12 and D13 multiplexed (ADS424x only) DA12M Refer to Figure 2 and DB0P, DB0M 2 Output Channel B differential output data pair, D0 and D1 multiplexed Figure 3 Refer to Figure 2 and DB2P, DB2M 2 Output Channel B differential output data D2 and D3 multiplexed Figure 3 Refer to Figure 2 and DB4P, DB4M 2 Output Channel B differential output data D4 and D5 multiplexed Figure 3 Refer to Figure 2 and DB6P, DB6M 2 Output Channel B differential output data D6 and D7 multiplexed Figure 3 Refer to Figure 2 and DB8P, DB8M 2 Output Channel B differential output data D8 and D9 multiplexed Figure 3 DB10P, Refer to Figure 2 and 2 Output Channel B differential output data D10 and D11 multiplexed DB10M Figure 3 DB12P, Refer to Figure 3 2 Output Channel B differential output data D12 and D13 multiplexed (ADS424x only) DB12M DRVDD 1, 48 2 Input Output buffer supply DRGND 49, PAD 2 Input Output buffer ground Refer to Figure 98, 8 (ADS422x) NC Figure 99, Figure 116, — Do not connect 4 (ADS424x) and Figure 117 Copyright © 2011, Texas Instruments Incorporated Submit Documentation Feedback 11 Product Folder Link(s): ADS4222 ADS4225 ADS4226 ADS4242 ADS4245 ADS4246 |
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