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4TPE470MCL bảng dữ liệu(PDF) 9 Page - Linear Technology

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LTM4600
9
4600fc
down when QDOWN is on and QUP is off. If the output
voltage VO needs to be margined up/down by ±M%, the
resistor values of RUP and RDOWN can be calculated from
the following equations:
(RSET RUP)• VO •(1+M%)
(RSET RUP)+ 100k
= 0.6V
RSET •VO •(1–M%)
RSET +(100k RDOWN)
= 0.6V
Input Capacitors
The LTM4600 μModule should be connected to a low
ac-impedance DC source. High frequency, low ESR input
capacitors are required to be placed adjacent to the mod-
ule. In Figure 18, the bulk input capacitor CIN is selected
for its ability to handle the large RMS current into the
converter. For a buck converter, the switching duty-cycle
can be estimated as:
D
=
VO
VIN
Without considering the inductor current ripple, the RMS
current of the input capacitor can be estimated as:
ICIN(RMS) =
IO(MAX)
%
•D •(1 D)
In the above equation, η% is the estimated efficiency of
the power module. C1 can be a switcher-rated electrolytic
aluminum capacitor, OS-CON capacitor or high volume
ceramic capacitors. Note the capacitor ripple current
ratings are often based on only 2000 hours of life. This
makes it advisable to properly derate the input capacitor,
or choose a capacitor rated at a higher temperature than
required. Always contact the capacitor manufacturer for
derating requirements.
In Figure 18, the input capacitors are used as high fre-
quency input decoupling capacitors. In a typical 10A
output application, 1-2 pieces of very low ESR X5R or
X7R, 10μF ceramic capacitors are recommended. This
decoupling capacitor should be placed directly adjacent
The typical LTM4600 application circuit is shown in Figure
18. External component selection is primarily determined
by the maximum load current and output voltage.
Output Voltage Programming and Margining
The PWM controller of the LTM4600 has an internal
0.6V±1% reference voltage. As shown in the block dia-
gram, a 100k/0.5% internal feedback resistor connects
VOUT and VOSET pins. Adding a resistor RSET from VOSET
pin to SGND pin programs the output voltage:
VO = 0.6V •
100k
+RSET
RSET
Table 1 shows the standard values of 1% RSET resistor
for typical output voltages:
Table 1.
RSET
(kΩ)
Open
100
66.5
49.9
43.2
31.6
22.1
13.7
VO
(V)
0.6
1.2
1.5
1.8
2
2.5
3.3
5
Voltage margining is the dynamic adjustment of the output
voltage to its worst case operating range in production
testing to stress the load circuitry, verify control/protec-
tion functionality of the board and improve the system
reliability. Figure 2 shows how to implement margining
function with the LTM4600. In addition to the feedback
resistor RSET, several external components are added.
Turn off both transistor QUP and QDOWN to disable the
margining. When QUP is on and QDOWN is off, the output
voltage is margined up. The output voltage is margined
Figure 2. LTM4600 Margining Implementation
PGND
SGND
4600 F02
LTM4600
VOUT
VOSET
RSET
RUP
QUP
100k
2N7002
RDOWN
QDOWN
2N7002
APPLICATIONS INFORMATION


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