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LC78857V bảng dữ liệu(PDF) 8 Page - Sanyo Semicon Device |
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LC78857V bảng dữ liệu(HTML) 8 Page - Sanyo Semicon Device |
8 / 11 page 3. Initialization This IC requires initialization when power is first applied and for system operation switching. After the power-supply voltage has stabilized and XIN, BCLK, and LRCK have been supplied, initialization is achieved by holding the INITB pin at the low level for at least one LRCK period as shown in the figure below. When INITB is low, the digital filter outputs and the noise shaper (sigma-delta D/A converter) internal states are all set to 0, and the analog outputs (OUTL and OUTR) go to the zero cross level. System Clock The LC78857V operates from a 384fs system clock. The 384fs system clock is generated using a crystal oscillator circuit consisting of a crystal element, resistors, and capacitors as shown in the figure. Optimal values for the resistors and capacitances depend on the peripheral circuits and other conditions. The sigma-delta D/A converter is a sensitive circuit, and the analog characteristics are strongly influenced by the quality of the waveform (e.g. its jitter characteristics) of the system clock input to the XIN pin. When an external signal is input as the system clock, adequate care must be taken to assure the quality of this signal's waveform. · CKO: Outputs a clock signal with the same frequency as the signal input to the XIN pin. Digital Filter Characteristics 1. Frequency characteristics · Normal speed (deemphasis off) No. 5537-8/11 LC78857V At least 1 LRCK period Crystal: 16.9344 MHz when fs = 44.1 kHz Sampling frequency, fs Supply voltage Crystal |
Số phần tương tự - LC78857V |
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Mô tả tương tự - LC78857V |
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