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LC78624E bảng dữ liệu(PDF) 3 Page - Sanyo Semicon Device |
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LC78624E bảng dữ liệu(HTML) 3 Page - Sanyo Semicon Device |
3 / 27 page No. 5811-3/27 LC78624E Specifications Absolute Maximum Ratings at Ta = 25°C, VSS = 0 V Parameter Symbol Conditions Ratings Unit Maximum supply voltage VDD max VSS – 0.3 to VSS + 7.0 V Input voltage VIN VSS – 0.3 to VDD + 0.3 V Output voltage VOUT VSS – 0.3 to VDD + 0.3 V Allowable power dissipation Pd max 300 mW Operating temperature Topr –20 to +75 °C Storage temperature Tstg –40 to +125 °C Parameter Symbol Conditions Ratings Unit min typ max VDD (1) VDD, XVDD, VVDD: 3.0 5.5 V During normal-speed playback Supply voltage VDD (2) VDD, XVDD, VVDD: 3.0 5.5 V During double-speed playback VIH (1) DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, Input high level voltage TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK 0.7 VDD VDD V VIH (2) EFMIN 0.6 VDD VDD V VIL (1) DEFI, COIN, RES, HFL, TES, SBCK, RWC, CQCK, Input low level voltage TAI, TEST1 to TEST6, CS, CONT1 to CONT5, SCLK 0 0.3 VDD V VIL (2) EFMIN 0 0.4 VDD V Data setup time tSU COIN, RWC: Figure 1 400 ns Data hold time tHD COIN, RWC: Figure 1 400 ns High level clock pulse width tWH SBCK, CQCK: Figures 1, 2 and 3 400 ns Low level clock pulse width tWL SBCK, CQCK: Figures 1, 2 and 3 400 ns Data read access time tRAC SQOUT, PW: Figures 2 and 3 0 400 ns Command transfer time tRWC RWC: Figure 1 1000 ns Subcode Q read enable time tSQE WRQ: Figure 2, with no RWC signal 11.2 ms Subcode read cycle time tSC SFSY: Figure 3 136 µs Subcode read enable time tSE SFSY: Figure 3 400 ns Port input data setup time tCSU CONT1 to CONT5, RWC: Figure 4 400 ns Port input data hold time tCHD CONT1 to CONT5, RWC: Figure 4 400 ns Port input clock setup time tRCQ RWC, CQCK: Figure 4 100 ns Port output data delay time tCDD CONT1 to CONT5, RWC: Figure 5 1200 ns Input level VIN (1) EFMIN: Slice level control 1.0 Vp-p VIN (2) XIN: Capacitor-coupled input 1.0 Vp-p Operating frequency range fop EFMIN 10 MHz Crystal oscillator frequency fX XIN, XOUT 16.9344 MHz Text readout time tCW DQSY : Figure 6. 1.5 3.3 3.7 ms DQSY pulse width tW DQSY : Figure 6. 60 136 150 µs SCLK “low” level pulse width tWTL SCLK : Figure 6. 100 ns SCLK “high” level pulse width tWTH SCLK : Figure 6. 100 ns SCLK delay time tD1 SCLK : Figure 6. 100 ns Text data delay time tD2 SRDT : Figure 6. 50 ns tD3 SRDT : Figure 6. 50 ns Reset time tRES RES 400 ns Allowable Operating Ranges at Ta = 25°C, VSS = 0 V |
Số phần tương tự - LC78624E |
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Mô tả tương tự - LC78624E |
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