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ADXRS453 bảng dữ liệu(PDF) 6 Page - Analog Devices

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ADXRS453
Rev. 0 | Page 6 of 32
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TOP VIEW
(Not to Scale)
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BACK VIEW
(Not to Scale)
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Figure 4. Pin Configuration, 14-Terminal LCC_V (Vertical Layout)
Figure 5. Pin Configuration, 14-Terminal LCC_V (Horizontal Layout)
Table 5. Pin Function Descriptions, 14-Terminal LCC_V
Pin No.
Mnemonic
Description
1
AVSS
Analog Ground.
2
AVDD
Analog Regulated Voltage. See Figure 27 for the application circuit diagram.
3
MISO
Master In/Slave Out.
4
DVDD
Digital Regulated Voltage. See Figure 27 for the application circuit diagram.
5
SCLK
SPI Clock.
6
CP5
High Voltage Supply. See Figure 27 for the application circuit diagram.
7
RSVD
Reserved. This pin must be connected to DVSS.
8
RSVD
Reserved. This pin must be connected to DVSS.
9
VX
High Voltage Switching Node. See Figure 27 for the application circuit diagram.
10
CS
Chip Select.
11
DVSS
Digital Signal Ground.
12
MOSI
Master Out/Slave In.
13
PSS
Switching Regulator Ground.
14
PDD
Supply Voltage.


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