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ADF7241 bảng dữ liệu(PDF) 9 Page - Analog Devices |
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ADF7241 bảng dữ liệu(HTML) 9 Page - Analog Devices |
9 / 72 page ADF7241 Rev. 0 | Page 9 of 72 CURRENT CONSUMPTION SPECIFICATIONS Table 6. Parameter Min Typ Max Unit Test Conditions CURRENT CONSUMPTION TX Mode Current Consumption −20 dBm 16.5 mA IEEE 802.15.4-2006 continuous packet transmission mode −10 dBm 17.4 mA IEEE 802.15.4-2006 continuous packet transmission mode 0 dBm 19.6 mA IEEE 802.15.4-2006 continuous packet transmission mode +3 dBm 21.5 mA IEEE 802.15.4-2006 continuous packet transmission mode +4 dBm 25 mA IEEE 802.15.4-2006 continuous packet transmission mode Idle Mode 1.8 mA XTO26M + digital active PHY_RDY Mode 10 mA RX Mode Current Consumption 19 mA IEEE 802.15.4-2006 packet mode MEAS State 3 mA SLEEP_BBRAM 0.3 μA BBRAM contents retained SLEEP_BBRAM_RCO 1 μA 32 kHz RC oscillator running, some BBRAM contents retained, wake-up time enabled SLEEP_BBRAM_XTO 1.7 μA 32 kHz crystal oscillator running, some BBRAM contents retained, wake-up time enabled TIMING AND DIGITAL SPECIFICATIONS Table 7. Logic Levels Parameter Min Typ Max Unit Test Conditions LOGIC INPUTS Input High Voltage, VINH 0.7 × VDD_BAT V Input Low Voltage, VINL 0.2 × VDD V Input Current, IINH/IINL ±1 μA Input Capacitance, CIN 10 pF LOGIC OUTPUTS Output High Voltage, VOH VDD_BAT − 0.4 V IOH = 500 μA Output Low Voltage, VOL 0.4 V IOL = 500 μA Output Rise/Fall 5 ns Output Load 7 pF Table 8. GPIOs Parameter Min Typ Max Unit Test Conditions GPIO OUTPUTS Output Drive Level 5 mA All GPIOs in logic high state Output Drive Level 5 mA All GPIOs in logic low state Table 9. SPI Interface Timing Parameter Min Typ Max Unit Description t1 15 ns CS falling edge to MISO setup time (TRX active) t2 40 ns CS to SCLK setup time t3 40 ns SCLK high time t4 40 ns SCLK low time t5 80 ns SCLK period t6 10 ns SCLK falling edge to MISO delay t7 5 ns MOSI to SCLK rising edge setup time t8 5 ns MOSI to SCLK rising edge hold time |
Số phần tương tự - ADF7241 |
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Mô tả tương tự - ADF7241 |
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