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LC4104C bảng dữ liệu(PDF) 3 Page - Sanyo Semicon Device |
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LC4104C bảng dữ liệu(HTML) 3 Page - Sanyo Semicon Device |
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3 / 9 page  Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V Note: V0, V2, V3, and V5 must obey the following inequalities: VDDH ≥ V0 ≥ V2 ≥ VDDH – 7 V, and 7 V ≥ V3 ≥ V5 ≥ VSS. At power on: First turn on the logic system power supply and then turn on the high-voltage system power supply. At power off: First turn off the high-voltage system power supply and then turn off the logic system power supply. Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 5 V ± 10% Note: * The clock rise time (tr) and fall time (tf) must obey inequalities and y below. : tr, tf < y: tr, tf ≤ 50 ns Allowable Operating Ranges at Ta = –20 to +75°C, VSS = 0 V, VDD = 2.7 to 4.5 V Note: * The clock rise time (tr) and fall time (tf) must obey inequalities and y below. : tr, tf < y: tr, tf ≤ 50 ns 1 – tw (cph) – tw (cpl) fcp 2 1 – tw (cph) – tw (cpl) fcp 2 No. 5194-3/9 LC4104C Parameter Symbol Conditions min typ max Unit Supply voltage VDD 2.7 5.5 V Supply voltage VDDH 20 36 V Supply voltage VSS 0 V Input high-level voltage VIH D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, 0.8 VDD VDD V EIO1, EIO2 Input low-level voltage VIL D0 to D7, LOAD, CP, R/L, M, TEST, DISP, BS, 0 0.2 VDD V EIO1, EIO2 Input voltage V0, V2 V0, V2 VDDH – 7 VDDH V Input voltage V3 V3 0 VSSH + 7 V Input voltage V5 V5 0 V Parameter Symbol Conditions min typ max Unit CP clock frequency fcp CP 12 MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 20 ns Low-level clock pulse width tw (cpL) CP 20 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 10 ns DATA/CP hold time tho (cp) CP, D0 to D7 10 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 24 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns Parameter Symbol Conditions min typ max Unit CP clock frequency fcp CP 10 MHz High-level load pulse width tw (ldH) LOAD 50 ns High-level clock pulse width tw (cpH) CP 37 ns Low-level clock pulse width tw (cpL) CP 37 ns LOAD/CP setup time tsu (ld) LOAD, CP 100 ns LOAD/CP hold time tho (ld) LOAD, CP 200 ns DATA/CP setup time tsu (cp) CP, D0 to D7 35 ns DATA/CP hold time tho (cp) CP, D0 to D7 35 ns EIO input setup time tsu (ei) CP, EIO1, EIO2 30 ns Clock rise time tr LOAD, CP* 50 ns Clock fall time tf LOAD, CP* 50 ns |
Số phần tương tự - LC4104C |
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Mô tả tương tự - LC4104C |
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