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LC36256AML-70 bảng dữ liệu(PDF) 6 Page - Sanyo Semicon Device |
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LC36256AML-70 bảng dữ liệu(HTML) 6 Page - Sanyo Semicon Device |
6 / 7 page LC36256AL, AML-70/85/10/12 No. 4163-6/7 • Write Cycle (2): CE Control Note (6) Notes (1) tCOD, tOOD, and tWOD are defined as the time at which the outputs becomes the high impedance state and are not referred to output voltage levels. (2) An external antiphase signal must not be applied when DOUT is in the output state. (3) tWP is the time interval that CE and WE are low-level and is defined as the interval from the falling of WE to the rising of CE or WE whichever is earlier. (4) tCW is the time interval that CE and WE are low-level and is defined as the time from the falling of CE to the rising of CE or WE whichever is earlier. (5) DOUT goes to the high-impedance state when either OE is high-level, CE is high-level, or WE is low-level. (6) When OE is high-level during the write cycle, DOUT goes to the high-impedance state. Data Retention Characteristics at Ta = 0 to +70°C Parameter Symbol Conditions min typ* max Unit Data retention supply voltage VDR VCE ≥ VCC–0.2V 2.0 5.5 V VCC = 3.0V, 0 to +70°C 10 ICCDR1 VCE ≥ 2.8V 0 to +40°C 2 µA Data retention supply current 25°C 0.25 1 ICCDR2 VCC = 2.0 to 5.5V, VCE ≥ VCC–0.2V 0.5 25 µA CE setup time tCDR 0 ns CE hold time tR tRC** ns * Reference values at VCC = 5V, Ta = 25°C ** tRC = Read Cycle time Data Retention Waveform |
Số phần tương tự - LC36256AML-70 |
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Mô tả tương tự - LC36256AML-70 |
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