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LM27402MH bảng dữ liệu(PDF) 11 Page - National Semiconductor (TI) |
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LM27402MH bảng dữ liệu(HTML) 11 Page - National Semiconductor (TI) |
11 / 32 page Theory of Operation GENERAL INFORMATION The LM27402 is a single-phase synchronous voltage mode DC/DC buck controller. The inductor DCR sense capability and integrated low impedance gate drivers allow the LM27402 to be used in high current, high power density ap- plications. Multiple fault conditions are supported including over-voltage, under-voltage, over-temperature, and over-cur- rent. The switching frequency can be adjusted over a wide range either by connecting a clock signal to SYNC pin or a resistor from FADJ to GND. The LM27402 supports pre-bi- ased outputs while maintaining synchronous mode operation. Input voltage feed-forward is incorporated into the control loop to mitigate the effects of input voltage variation. UVLO An under-voltage lockout is built into the LM27402 which al- lows the device to only switch if the input voltage (VIN) and the internal sub-regulated voltage (VDD) both exceed 2.9V. A 300mV UVLO hysteresis exists on both VDD and VIN to prevent power on and off anomalies related to input voltage deviations. PRECISION ENABLE (EN) The enable pin of the LM27402 allows the output to be toggled on and off and is a precision analog input. When the EN volt- age exceeds 1.17V, the controller will initiate the soft-start sequence as long as the input voltage and sub-regulated volt- age have exceeded their UVLO thresholds of 2.9V. The EN pin has an absolute maximum voltage rating of 6.0V and should not exceed the voltage on VDD. There is an internal 2 µA pull-up current source connected to the EN pin. If EN is open, the LM27402 will turn on automatically if VIN and VDD exceed 2.9V. If the EN voltage is held below 0.8V, the LM27402 enters a deep shutdown state where the internal bias circuitry is off. The quiescent current is approximately 35 µA in deep shutdown. The EN pin has 100mV of hysteresis to reject noise and allow the pin to be resistively coupled to the input voltage or sequenced with other rails. SOFT-START AND VOLTAGE TRACKING (SS/TRACK) When the enable pin has exceeded 1.17V and both VIN and VDD have exceeded their UVLO thresholds, the LM27402 will begin charging the output linearly to the voltage level dictated by the feedback resistor network. The soft-start time is set by connecting a capacitor from SS/TRACK to GND. After EN exceeds 1.17V, an internal 3 µA current source begins to lin- early charge the soft-start capacitor. Soft-start allows the user to limit inrush currents related to high output capacitance and output slew rate. If a soft-start capacitor is not used, the LM27402 defaults to a 1.28 ms digitally controlled startup time. The SS/TRACK pin can also be used to ratiometrically or coincidentally track an external voltage source. See the SETTING THE SOFT-START TIME and TRACKING sections of the design guide for more information. PRE-BIAS STARTUP In certain applications, the output may acquire a pre-bias volt- age before the LM27402 is powered on or enabled. Pre- biased conditions are managed by preventing switching until the soft-start (SS/TRACK) voltage exceeds the feedback (FB) voltage. Once V SS/TRACK has exceeded VFB, the LM27402 will begin to switch synchronously and regulate the output volt- age. 30092645 FIGURE 1. Pre-Bias Startup Prohibiting switching during a pre-biased startup condition prevents the output from forcing parasitic paths to conduct excessive current. The LM27402 will not switch if the output is pre-biased to a voltage higher than the nominally set output voltage. CURRENT LIMIT The LM27402 may enter two states when a current limit event is detected. If a current limit condition has occurred, the high- side FET is immediately turned off until the next switching cycle. This is considered the first current limit state and pro- vides an immediate response to any current limit event. Dur- ing the first state, an internal counter will begin to record the number of over-current events. The counter is reset if 32 con- secutive switching cycles occur with no current limit events detected. If five over-current events are detected within 32 switching cycles, the LM27402 then enters into a hiccup mode state. During hiccup mode, the LM27402 will shutdown for 1.28 ms and then attempt to restart again. When transitioning into hiccup mode, the high-side FET is turned off and the low- side FET is turned on. As the inductor current reaches zero subsequent to the over-current event, the low-side FET is turned off and the switch-node becomes high impedance to prepare for the next startup sequence. The soft-start capaci- tor is discharged through an internal pull-down FET to reini- tialize the startup sequence. To illustrate how the LM27402 behaves during current limit faults, an over-current scenario is illustrated in Figure 2. 11 www.national.com |
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