5

FN8231.9

November 30, 2010

Timing Diagrams

Bus Timing

STOP Condition Set-up Time

From SCL rising edge crossing 70%

600

ns

STOP Condition Hold Time for

Read or Volatile Only Write

From SDA rising edge to SCL falling

600

ns

Output Data Hold Time

From SCL falling edge crossing 30%

0ns

Cpin

SDA and SCL Pin Capacitance

10

pF

Non-volatile Write Cycle Time

12

20

ms

14

SDA and SCL Rise Time

20 + 0.1xCb

300

ns

SDA and SCL Fall Time

20 +0.1xCb

300

ns

15

Cb

Capacitive Loading of SDA or SCL Total on-chip and off-chip

10

400

pF

15

SDA and SCL Bus Pull-up Resistor

Off-chip

For Cb = 400pF, max is about

2k

Ω~2.5kΩ.

For Cb = 40pF, max is about

15k

Ω~20kΩ

1k

Ω

15

NOTES:

11. Specified at +25°C.

13. Parameter is not 100% tested.

sequence of a serial interface Write operation, to the end of the self-timed internal non-volatile write cycle.

16. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.

AC Electrical Specifications

(Continued)

SYMBOL

PARAMETER

TEST CONDITIONS

MIN

(Note 16)

TYP

MAX

(Note 16)

UNITS

NOTES

SCL

SDA

(INPUT TIMING)

SDA

(OUTPUT TIMING)

ISL12026, ISL12026A