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SI1013 bảng dữ liệu(PDF) 10 Page - Silicon Laboratories

tên linh kiện SI1013
Giải thích chi tiết về linh kiện  Ultra Low Power, 16/8 kB, 12/10-Bit ADC MCU with Integrated 240-960 MHz EZRadioPRO Transceiver
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nhà sản xuất  SILABS [Silicon Laboratories]
Trang chủ  http://www.silabs.com
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SI1013 bảng dữ liệu(HTML) 10 Page - Silicon Laboratories

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Si1010/1/2/3/4/5
10
Rev. 1.0
List of Figures
Figure 1.1. Si1010 Block Diagram ........................................................................... 21
Figure 1.2. Si1011 Block Diagram ........................................................................... 21
Figure 1.3. Si1012 Block Diagram ........................................................................... 22
Figure 1.4. Si1013 Block Diagram ........................................................................... 22
Figure 1.5. Si1014 Block Diagram ........................................................................... 23
Figure 1.6. Si1015 Block Diagram ........................................................................... 23
Figure 1.7. Si1012/3 RX/TX Direct-tie Application Example .................................... 24
Figure 1.8. Si1010/1 Antenna Diversity Application Example ................................. 24
Figure 1.9. Port I/O Functional Block Diagram ........................................................ 26
Figure 1.10. PCA Block Diagram ............................................................................. 27
Figure 1.11. ADC0 Functional Block Diagram ......................................................... 28
Figure 1.12. ADC0 Multiplexer Block Diagram ........................................................ 29
Figure 1.13. Comparator 0 Functional Block Diagram ............................................ 30
Figure 1.14. Comparator 1 Functional Block Diagram ............................................ 30
Figure 3.1. Si1010/1/2/3 Pinout Diagram (Top View) .............................................. 36
Figure 3.2. Si1004/5 Pinout Diagram (Top View) .................................................... 37
Figure 3.3. QFN-42 Package Drawing .................................................................... 38
Figure 3.4. Typical QFN-42 Landing Diagram ......................................................... 40
Figure 3.5. VIA Placement and Keepout Region ..................................................... 41
Figure 3.6. Typical PCB Stencil Diagram ................................................................ 42
Figure 4.1. Active Mode Current (External CMOS Clock) ....................................... 49
Figure 4.2. Idle Mode Current (External CMOS Clock) ........................................... 50
Figure 4.3. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 2 V) .. 51
Figure 4.4. Typical DC-DC Converter Efficiency (High Current, VDD/DC+ = 3 V) .. 52
Figure 4.5. Typical DC-DC Converter Efficiency (Low Current, VDD/DC+ = 2 V) ... 53
Figure 4.6. Typical One-Cell Suspend Mode Current .............................................. 54
Figure 4.7. Typical VOH Curves, 1.8–3.6 V ............................................................ 56
Figure 4.8. Typical VOH Curves, 0.9–1.8 V ............................................................ 57
Figure 4.9. Typical VOL Curves, 1.8–3.6 V ............................................................. 58
Figure 4.10. Typical VOL Curves, 0.9–1.8 V ........................................................... 59
Figure 5.1. ADC0 Functional Block Diagram ........................................................... 77
Figure 5.2. 10-Bit ADC Track and Conversion Example Timing (BURSTEN = 0) ... 80
Figure 5.3. Burst Mode Tracking Example with Repeat Count Set to 4 .................. 81
Figure 5.4. ADC0 Equivalent Input Circuits ............................................................. 82
Figure 5.5. ADC Window Compare Example: Right-Justified Single-Ended Data .. 93
Figure 5.6. ADC Window Compare Example: Left-Justified Single-Ended Data ..... 93
Figure 5.7. ADC0 Multiplexer Block Diagram .......................................................... 94
Figure 5.8. Temperature Sensor Transfer Function ................................................ 96
Figure 5.9. Temperature Sensor Error with 1-Point Calibration (VREF = 1.68 V) .... 97
Figure 5.10. Voltage Reference Functional Block Diagram ..................................... 99
Figure 7.1. Comparator 0 Functional Block Diagram ............................................ 104
Figure 7.2. Comparator 1 Functional Block Diagram ............................................ 105
Figure 7.3. Comparator Hysteresis Plot ................................................................ 106


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