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8 / 60 page Rev. PrA | Page 8 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data Note that the external memory bank addresses shown are for normal-word (32-bit) accesses. If 48-bit instructions as well as 32-bit data are both placed in the same external memory bank, care must be taken while mapping them to avoid overlap. In case of 32-bit wide external memory, two 48-bit instructions will be stored in three 32-bit wide memory locations. For exam- ple, if 2k instructions are placed in 32-bit wide external memory starting at the bank 0 normal-word base address 0x0030 0000 (corresponding to instruction address 0x0020 0000) and ending at address 0x0030 0BFF (corresponding to instruction address 0x0020 07FF), then data buffers can be placed starting at an address that is offset by 3k 32-bit words (for example, starting at 0x0030 0C00). Asynchronous Memory Controller The asynchronous memory controller provides a configurable interface for up to four separate banks of memory or I/O devices. Each bank can be independently programmed with dif- ferent timing parameters, enabling connection to a wide variety of memory devices including SRAM, flash, and EPROM, as well as I/O devices that interface with standard memory control lines. Bank 0 occupies a 14M word window and banks 1, 2, and 3 occupy a 16M word window in the processor’s address space but, if not fully populated, these windows are not made contigu- ous by the memory controller logic. The asynchronous memory controller is capable of a maximum throughput of TBD Mbps using a TBD MHz external bus speed. Other features include 8 to 32-bit packing and unpacking, boot- ing from bank select 1, and support for delay line DMA. Shared External Memory The ADSP-21462W/ADSP-21465W/ADSP-21467 processor supports connecting to common shared external DDR2 mem- ory with other ADSP-2146x processors to create shared external bus processor systems. This support includes: • Distributed, on-chip arbitration for the shared external bus • Fixed and rotating priority bus arbitration • Bus time-out logic • Bus lock Multiple processors can share the external bus with no addi- tional arbitration logic. Arbitration logic is included on-chip to allow the connection of up to TBD processors. Bus arbitration is accomplished through the BR6-1 signals and the priority scheme for bus arbitration is determined by the set- ting of the RPBA pin. Table 6 on Page 13 provides descriptions of the pins used in multiprocessor systems. INPUT/OUTPUT FEATURES The ADSP-21462W and ADSP-21465W I/O processors provide 67 channels of DMA, while ADSP-21467 I/O processors pro- vide 36 channels of DMA as well as an extensive set of peripherals. These include a 20 lead digital applications inter- face, which controls: • Eight serial ports • S/PDIF receiver/transmitter • Four precision clock generators • Input data port/parallel data acquisition port • Four asynchronous sample rate converters The ADSP-21462W/ADSP-21465W/ADSP-21467 processor also contains a 14 lead digital peripheral interface, which controls: • Two general-purpose timers • Two serial peripheral interfaces • One universal asynchronous receiver/transmitter (UART) •An I2C®-compatible 2-wire interface • Two PCGs (C and D) can also be routed through DPI DMA Controller The processor’s on-chip DMA controller allows data transfers without processor intervention. The DMA controller operates independently and invisibly to the processor core, allowing DMA operations to occur while the core is simultaneously exe- cuting its program instructions. DMA transfers can occur between the ADSP-21462W/ADSP-21465W/ADSP-21467’s internal memory and its serial ports, the SPI-compatible (serial peripheral interface) ports, the IDP (input data port), the paral- lel data acquisition port (PDAP) or the UART. Sixty-seven channels of DMA are available on the ADSP-21462W and ADSP-21465W devices, and thirty-six channels on the ADSP-21467. The breakdown is as follows: 16 via the serial ports, eight via the input data port, two for the Table 5. External Memory for DDR2 DRAM Addresses Bank Size in Words Address Range Bank 0 62M 0x0020 0000 – 0x03FF FFFF Bank 1 64M 0x0400 0000 – 0x07FF FFFF Bank 2 64M 0x0800 0000 – 0x0BFF FFFF Bank 3 64M 0x0C00 0000 – 0x0FFF FFFF Table 4. External Memory for Non DDR2 DRAM Addresses Bank Size in Words Address Range Bank 0 14M 0x0020 0000 – 0x00FF FFFF Bank 1 16M 0x0400 0000 – 0x04FF FFFF Bank 2 16M 0x0800 0000 – 0x08FF FFFF Bank 3 16M 0x0C00 0000 – 0x0CFF FFFF |
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