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6 / 60 page  Rev. PrA | Page 6 of 60 | November 2008 ADSP-21462W/ADSP-21465W/ADSP-21467 Preliminary Technical Data data accesses are cached. This cache allows full speed execution of core, looped operations such as digital filter multiply-accu- mulates, and FFT butterfly processing. Data Address Generators With Zero-Overhead Hardware Circular Buffer Support The ADSP-21462W/ADSP-21465W/ADSP-21467’s two data address generators (DAGs) are used for indirect addressing and implementing circular data buffers in hardware. Circular buff- ers allow efficient programming of delay lines and other data structures required in digital signal processing, and are com- monly used in digital filters and Fourier transforms. The two DAGs of the processors contain sufficient registers to allow the creation of up to 32 circular buffers (16 primary register sets, 16 secondary). The DAGs automatically handle address pointer wraparound, reduce overhead, increase performance, and sim- plify implementation. Circular buffers can start and end at any memory location. Flexible Instruction Set The 48-bit instruction word accommodates a variety of parallel operations, for concise programming. For example, the ADSP-21462W/ADSP-21465W/ADSP-21467 can conditionally execute a multiply, an add, and a subtract in both processing elements while branching and fetching up to four 32-bit values from memory—all in a single instruction. Variable Instruction Set Architecture In addition to supporting the standard 48-bit instructions from previously existing SHARC family of processors, the ADSP- 21462W/ADSP-21465W/ADSP-21467 support new instruc- tions of 16 and 32 bits in addition to the existing 48 bit instructions. This feature, called Variable Instruction Set Archi- tecture (VISA), is based on dropping redundant/unused bits within the 48-bit instruction to create more efficient and com- pact code. The program sequencer will now support fetching these 16-bit and 32-bit instructions as well in addition to the standard 48-bit instructions, both from internal as well as exter- nal memory. Source modules will need to be built using the VISA option, in order to allow code generation tools to create these more efficient opcodes. FFT Accelerator FFT accelerator implements radix-2 complex/real input, com- plex output FFT with no core intervention. FIR Accelerators The FIR (finite impulse response) accelerator consists of a 1024 word coefficient memory, a 1024 word deep delay line for the data, and four MAC units. A controller manages the accelerator. The FIR accelerator runs at the peripheral clock frequency. IIR Accelerators The IIR (infinite impulse response) accelerator consists of a 1440 word coefficient memory for storage of biquad coeffi- cients, a data memory for storing the intermediate data and one MAC unit. A controller manages the accelerator. The IIR accel- erator runs at the peripheral clock frequency. MEMORY The ADSP-21462W/ADSP-21465W/ADSP-21467 adds the fol- lowing architectural features to the SIMD SHARC family core. On-Chip Memory The processors contain 5 Mbits of internal RAM. Each block can be configured for different combinations of code and data storage (see Table 3 on Page 7). Each memory block supports single-cycle, independent accesses by the core processor and I/O processor. The ADSP-21462W/ADSP-21465W/ADSP-21467 memory architecture, in combination with its separate on-chip buses, allow two data transfers from the core and one from the I/O processor, in a single cycle. The processor’s SRAM can be configured as a maximum of 160k words of 32-bit data, 320k words of 16-bit data, 106.7k words of 48-bit instructions (or 40-bit data), or combinations of different word sizes up to 5 megabit. All of the memory can be accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float- ing-point storage format is supported that effectively doubles the amount of data that may be stored on-chip. Conversion between the 32-bit floating-point and 16-bit floating-point for- mats is performed in a single instruction. While each memory block can store combinations of code and data, accesses are most efficient when one block stores data using the DM bus for transfers, and the other block stores instructions and data using the PM bus for transfers. Using the DM bus and PM buses, with one bus dedicated to a memory block, assures single-cycle execution with two data transfers. In this case, the instruction must be available in the cache. The memory map in Table 3 displays the internal memory address space of the ADSP-21462W/ADSP-21465W/ADSP- 21467. The 48-bit space section describes what this address range looks like to an instruction that retrieves 48-bit memory. The 32-bit section describes what this address range looks like to an instruction that retrieves 32-bit memory. EXTERNAL MEMORY The external port on the ADSP-21462W/ADSP- 21465W/ADSP-21467 SHARC provides a high performance, glueless interface to a wide variety of industry-standard memory devices. The external port may be used to interface to synchro- nous and/or asynchronous memory devices through the use of its separate internal DDR2 memory controller. The 16-bit DDR2 DRAM controller connects to industry-standard syn- chronous DRAM devices, while the second 8-bit asynchronous memory controller is intended to interface to a variety of mem- ory devices. Four memory select pins enable up to four separate devices to coexist, supporting any desired combination of syn- chronous and asynchronous device types. Non DDR2 DRAM external memory address space is shown in Table 4. |
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