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ISL1219IUZ bảng dữ liệu(PDF) 5 Page - Intersil Corporation |
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ISL1219IUZ bảng dữ liệu(HTML) 5 Page - Intersil Corporation |
5 / 24 page 5 FN6314.1 August 14, 2006 SDA vs. SCL Timing Symbol Table tF SDA and SCL Fall Time From 70% to 30% of VDD. 20 + 0.1 x Cb 300 ns 7 Cb Capacitive Loading of SDA or SCL Total on-chip and off-chip 10 400 pF 7 Rpu SDA and SCL Bus Pull-up Resistor Off-chip Maximum is determined by tR and tF. For Cb = 400pF, max is about 2~2.5k Ω. For Cb = 40pF, max is about 15~20k Ω 1k Ω 7 NOTES: 2. IRQ and FOUT and EVDET Inactive. 3. LPMODE = 0 (default). 4. In order to ensure proper timekeeping, the VDD SR- specification must be followed. 5. Typical values are for T = 25°C and 3.3V supply voltage. 6. VSUP = VDD if in VDD Mode, VSUP = VBAT if in VBAT Mode. 7. These are I2C specific parameters and are not directly tested, however they are used during device testing to validate device specification. 8. A write to register 08h should only be done if VDD > VBAT, otherwise the device will be unable to communicate using I 2C. I2C Interface Specifications Test Conditions: VDD = +2.7 to +5.5V, Temperature = -40°C to +85°C, unless otherwise specified. SYMBOL PARAMETER TEST CONDITIONS MIN TYP (Note 4) MAX UNITS NOTES tSU:STO tDH tHIGH tSU:STA tHD:STA tHD:DAT tSU:DAT SCL SDA (INPUT TIMING) SDA (OUTPUT TIMING) tF tLOW tBUF tAA tR WAVEFORM INPUTS OUTPUTS Must be steady Will be steady May change from LOW to HIGH Will change from LOW to HIGH May change from HIGH to LOW Will change from HIGH to LOW Don’t Care: Changes Allowed Changing: State Not Known N/A Center Line is High Impedance ISL1219 |
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Mô tả tương tự - ISL1219IUZ |
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